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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
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<link rel="stylesheet" href="css/mycss.css" type="text/css" />
<title>Sandeep Dasgupta</title>
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<body>
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<div id="header">
<div id="maincontent">
<div id="twocolleft">
<div id="name">Sandeep Dasgupta </div>
<div id="affiliation">PhD, Computer Science</div>
</div>
<div id="twocolright">
<img id="logo" width=239px src="logo/l1.gif">
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<div id="navi"> <a href="index.html"><div id="on">Home</div></a>
<a href="Resume/Resume_Job.pdf"><div id="on">Resume</div></a>
<a href="publication.html"><div id="on">Publication</div></a>
<a href="projects.html"><div id="on">Projects</div></a>
<a href="industry.html"><div id="on">Industry</div></a>
<a href="https://sdasgup3.github.io/"><div id="on">Blog</div></a>
<a href="hobbies.html"><div id="on">Hobbies</div></a>
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<div id="maincontent">
<div id="onecol">
<div id="subheader">Job Experience</div>
<ul> <a href=https://www.google.com/intl/en/about/>Google Inc.</a> <i>Software Engineering Intern, September 2018 - December 2018</i> <hr>
<ul>
<li>
Worked in <q>Google kernel performance</q>
team to augment the perf tools with
<a href=https://ieeexplore.ieee.org/document/6844459>Topdown
Analysis</a> capability.
</li>
<ul>
<li>
Intel developed a cycle decomposition
methodology called <a
href=https://ieeexplore.ieee.org/document/6844459>Topdown</a>.
It uses about 60 hardware events to
breakdown micro-architectural performance
bottlenecks encountered by running software
on Intel processors. It is very useful in
characterizing workloads and focusing on
where to apply optimizations. Topdown is
described as a tree of metrics, each one
requiring many events, and published as a
complex spreadsheet. The goal of the
project is to automate the conversion of
the formulas in the spreadsheet into C code
that can be integrated into the perf tool.
Today, this conversion is done by hand. As
the spreadsheet is constantly evolving to
support new hardware and tweak of the
formulas, we need an automated way of doing
the conversion. Such an automated converter
is realized in this project.
</li>
<li>
We developed tool <q>topdown_parser</q>
which takes as input, the topdown xlsx, and
generates C code to collect and report all
levels of topdown tree across all supported
processors. The tool is general enough to
emit code (encoding the topdown formulas)
for other projects like, <a
href=https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/tree/tools/perf>
Public perf tool</a>, in which case we emit json files encoding the topdown
metric expression.
</li>
</ul>
<li> Data Profiling to extract type
information from binaries. Given a set of
hot load/store instructions (generated by
sampling the application using tools like
perf), the problem is to find the type of
the data address associated with those
instructions. The found type information
(which can be referred to as hot types) are
useful in optimizing memory allocation
strategies or cache utilization. We developed
the following prototypes. </li>
<ul>
<li> Based on Allocation Based Profiling: We
generate samples of allocation information
(like allocation base address, size, etc) and
use that to find which allocation is feeding
a particular load/store data address. </li>
<li> Based on Dwarf debug Info: Dwarf debug
information stores, as a best effort, the
variables in a given scope along with its
associated type. The idea is to find which
variable, in load/store instruction's scope,
is getting consumed by a given load/store
data address. For that we needed to parse the
location list information of dwarf. </li>
</ul>
</ul>
<ul> <a href=https://www.google.com/intl/en/about/>Google Inc.</a> <i>Software Engineering Intern, May 2017 - August 2017</i> <hr>
<ul>
<li>
Worked in <q>Google continuous profiling and
efficiency</q> team to augment the profiling
tools with analysis capable of guiding the
service owners to pinpoint unexpected
performance changes (called <q>havocs</q> in
this work) in CPU time. Challenges are:
</li>
<ul>
<li> To determine <q>havocs</q> amid noisy data. </li>
<li> To reduce false positives and pinpoint actionable <q>havocs</q> to the service providers. </li>
</ul>
<li>
Investigated the effectiveness of existing strategies in literature and open source.
</li>
<li>
Developed a statistical Go tool which
determines potential <q>havocs</q> with
reduced false positive rate. Came up with an
idea of correlating the statistically
detected trend changes in the data with build
CL changes which not only gives confidence on
trend change detection but also helps in
reducing the false positives.
</li>
<li>
Carried out the research part of the project
independently aligning the milestones and the
work progress with the project supervisor.
Collaborated with the team on the details of
integrating with the data querying pipeline.
</li>
</ul>
</ul>
<ul> <a href=http://www.apple.com>Apple Inc., </a> <i> Compiler Engineer, PhD Intern, April 2016 - August 2016</i> <hr>
<ul>
<li>
Worked as a member of Swift Performance Team
on an exploratory project which requires
sound knowledge in compiler backend. Achieved
functional completeness with real work loads.
</li>
</ul></ul>
<ul> <a href=http://www.intel.in/content/www/in/en/homepage.html>Intel Technology India Pvt. Ltd., </a> <i> Component Design Engineer, August 2011 - June 2013</i> <hr>
<ul>
<li> Worked as Design Automation Engineer for Formal Equivalence Verification (FEV) of hardware designs. </li>
<li> Contributed to and supported Broadwell (BDX) and Skylake (SKL) FEV requirements. Played key role in FEV audit checks for BDX.
</li>
<li> Owner of tools and infrastructures for driving
FEV central runs for BDX. Worked closely with teams of various
design styles in understanding the requirements for
customization and also provided the much needed support for
successfully deploying those tools.
</li>
<li> Build flows and methodologies to provide solutions on how
to formally verify leading next generation CPU designs.
Interacted closely with global FEV teams to understand the
requirements and contributed to the success of various
sprints with timely and quality delivery on assignments.
</li>
</ul></ul>
<ul> <a href=http://www.interrasystems.com/>Interra Systems India Pvt. Ltd., </a> <i> Senior Member Of Technical Staff, August 2006 - July 2009</i> <hr>
<ul>
<li> Developer of Interra's premiere front-end analyzer products - Cheetah (SystemVerilog) and MVV(Mixed Verilog Vhdl) and
provided support for several new constructs of System Verilog IEEE-1800-2005, fixed tool bugs, created applications and contributed in performance Improvement.
</li>
<li> Involved in a critical service project for <a href=http://www.atrenta.com>Atrenta (I) Pvt. Ltd.</a> for the development of System Verilog features in Spyglass DFT.
</li>
</ul></ul>
</div>
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<strong>sdasgup3 [at] illinois [dot] edu</strong> <br \>
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