From 3daf898efc8cc98288f6f5d584721362bdbeb03a Mon Sep 17 00:00:00 2001
From: Alexander Romanov <alex.rom23@mail.ru>
Date: Wed, 17 Apr 2024 12:40:40 +0300
Subject: [PATCH] feat(countcomb): working switches gp

---
 projects/chisel-practice/boards/tangnano9k.cst        | 11 +++++++++++
 .../src/main/scala/projects/CountCombinations.scala   | 11 +++++++----
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/projects/chisel-practice/boards/tangnano9k.cst b/projects/chisel-practice/boards/tangnano9k.cst
index f9cc011..8ba1d15 100644
--- a/projects/chisel-practice/boards/tangnano9k.cst
+++ b/projects/chisel-practice/boards/tangnano9k.cst
@@ -3,6 +3,17 @@
 // https://github.com/YosysHQ/apicula/blob/master/examples/tangnano9k.cst
 // Part Number: GW1NR-LV9QN88PC6/I5
 
+IO_LOC "io_switchNumber[0]" 33; 
+IO_LOC "io_switchNumber[1]" 30;
+IO_LOC "io_switchNumber[2]" 29;
+IO_LOC "io_switchNumber[3]" 28;
+IO_LOC "io_switchNumber[4]" 26;
+IO_LOC "io_switchNumber[5]" 25;
+IO_LOC "io_switchNumber[6]" 39;
+IO_LOC "io_switchNumber[7]" 36;
+
+IO_LOC "io_switch" 41;
+
 IO_LOC "io_led[0]" 76;
 IO_LOC "io_led[1]" 38;
 IO_LOC "io_led[2]" 37;
diff --git a/projects/chisel-practice/src/main/scala/projects/CountCombinations.scala b/projects/chisel-practice/src/main/scala/projects/CountCombinations.scala
index cc8a6a9..8329e39 100644
--- a/projects/chisel-practice/src/main/scala/projects/CountCombinations.scala
+++ b/projects/chisel-practice/src/main/scala/projects/CountCombinations.scala
@@ -27,6 +27,8 @@ class CountCombinationsTopIO(numDigits: Int, numLeds: Int) extends Bundle {
   val digit = Output(UInt(numDigits.W))
   val led = Output(UInt(numLeds.W))
   val segments = Output(UInt(8.W))
+  val switchNumber = Input(UInt(numLeds.W))
+  val switch = Input(Bool())
 }
 
 class CountCombinationsTop(
@@ -42,10 +44,11 @@ class CountCombinationsTop(
   val dividedClock = withReset(reset = false.B) {
     ClockDivider(clock, countFreq)
   }
-  val (value, _) =
+  val (valueTmp, _) =
     withClockAndReset(clock = dividedClock, reset = invertedReset) {
       Counter(true.B, countMax)
     }
+
   val top = withReset(reset = invertedReset) {
     Module(new CountCombinations(numBits))
   }
@@ -55,14 +58,14 @@ class CountCombinationsTop(
   io.digit <> sevenseg.io.digitSelect
   io.segments <> sevenseg.io.segments
   sevenseg.io.value := top.io.count
-  top.io.value := value
-  io.led := value
+  io.led := Mux(io.switch, ~io.switchNumber, valueTmp)
+  top.io.value := Mux(io.switch, ~io.switchNumber, valueTmp)
 }
 
 object CountCombinationsVerilog extends App {
   ChiselStage.emitSystemVerilogFile(
     new CountCombinationsTop(8 /* numBits */, 4 /* numDigits */,
-      8 /* numLeds */, 135_000, 5_000_000, 256),
+      8 /* numLeds */, 135_000, 50_000_000, 256),
     args = Array("--target-dir", "generated/projects"),
     firtoolOpts = Array(
       "--disable-all-randomization",