feat(chisel-practice): add "projects" package

serjzimmerman · Apr 13, 2024 · 78aa017 · 78aa017
1 parent 7b4563b
commit 78aa017
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Showing 3 changed files with 35 additions and 2 deletions.
diff --git a/projects/chisel-practice/Makefile b/projects/chisel-practice/Makefile
@@ -11,7 +11,7 @@ NEXTPNR_FREQ = 27.00
 .DEFAULT_GOAL := all
 .PHONY := clean all
 
-all: blinky.fs sevenseg.fs
+all: blinky.fs sevenseg.fs countcomb.fs
 
 generated/blinky/Top.sv:
 	$(SBT) "runMain blinky.BlinkyVerilog"
@@ -39,5 +39,18 @@ pnrsevenseg.json: sevenseg.json
 sevenseg.fs: pnrsevenseg.json
 	$(APICULA) -d $(NEXTPNR_FAMILY) -o sevenseg.fs pnrsevenseg.json
 
+generated/projects/SevenSegTop.sv: ./src/main/scala/projects/CountCombinations.scala
+	$(SBT) "runMain projects.CountCombinationsVerilog"
+
+countcomb.json: generated/projects/SevenSegTop.sv
+	$(YOSYS) -p "read_verilog -sv generated/projects/SevenSegTop.sv; synth_gowin -json countcomb.json"
+
+pnrcountcomb.json: countcomb.json
+	$(NEXTPNR) --freq $(NEXTPNR_FREQ) --json countcomb.json --write pnrcountcomb.json --device $(NEXTPNR_DEVICE) \
+	--family $(NEXTPNR_FAMILY) --cst boards/tangnano9k.cst
+
+countcomb.fs: pnrcountcomb.json
+	$(APICULA) -d $(NEXTPNR_FAMILY) -o countcomb.fs pnrcountcomb.json
+
 clean:
 	rm -rf target/ *.fs *.json generated/
diff --git a/projects/chisel-practice/src/main/scala/blinky/SevenSeg.scala b/projects/chisel-practice/src/main/scala/blinky/SevenSeg.scala
@@ -85,7 +85,7 @@ class SevenSegTop(
 
 object SevenSegVerilog extends App {
   ChiselStage.emitSystemVerilogFile(
-    new SevenSegTop(4, 6, 270_000, 2_700_000, 128),
+    new SevenSegTop(4, 6, 270_000, 2_700_000, 0xffff),
     args = Array("--target-dir", "generated/blinky"),
     firtoolOpts = Array(
       "--disable-all-randomization",

diff --git a/projects/chisel-practice/src/main/scala/projects/CountCombinations.scala b/projects/chisel-practice/src/main/scala/projects/CountCombinations.scala
@@ -0,0 +1,20 @@
+package projects
+
+import util.ClockDivider
+import blinky.SevenSegTop
+import chisel3._
+import chisel3.util.Counter
+import circt.stage.ChiselStage
+
+
+object CountCombinationsVerilog extends App {
+  ChiselStage.emitSystemVerilogFile(
+    new SevenSegTop(4, 6, 270_000, 2_700_000, 0xffff),
+    args = Array("--target-dir", "generated/projects"),
+    firtoolOpts = Array(
+      "--disable-all-randomization",
+      "--strip-debug-info",
+      "--lowering-options=disallowLocalVariables,disallowPackedArrays"
+    )
+  )
+}