chapter 8

.gitattributes

@@ -1,2 +1,15 @@
 
-dependencies/* linguist-vendored
+# EOL
+*                   text eol=lf
+dependencies/*      -text
+dependencies/**/*   -text
+media/graphics/*    -text
+media/graphics/**/* -text
+
+# Language Corrections
+*.vh                linguist-language=Verilog
+*.core              linguist-language=YAML
+
+# Vendored
+dependencies/*      linguist-vendored
+dependencies/**/*   linguist-vendored

README.md

@@ -1,5 +1,20 @@
 # Thesis
 
+## Cite
+
+If you use this thesis in your research, please include the following citation:
+
+```bibtex
+@mastersthesis{SiffermanMastersThesis,
+  author = {Sifferman, Ethan},
+  title = {{A}dvancing {S}ynthesizable {V}erilog/{S}ystem{V}erilog {E}ducation with {O}pen-{S}ource {T}ools and {A}utograders},
+  school = {University of California, Santa Barbara},
+  month = {September},
+  year = {2023},
+  note = {\url{https://thesis.sifferman.dev/}},
+}
+```
+
 ## Build Instructions
 
 ```bash

tex/chapters/3_digital_design.tex

@@ -27,7 +27,7 @@ \section{Rely on style guides for synthesizable SystemVerilog.}
 
 \input{figures/dc_vs_synplify}
 
-RTL engineers use C-like constructs [gloss] such as procedural blocks, \mintinline{systemverilog}{for} loops, and \mintinline{systemverilog}{if} statements from Verilog; and \mintinline{systemverilog}{struct}, \mintinline{systemverilog}{union}, and \mintinline{systemverilog}{enum} constructs from SystemVerilog. To promote uniformity among tools, IEEE standardized synthesis of Verilog 1364 features under the label ``1364.1". However, there has been no official ``1800.1" SystemVerilog synthesis standard to discuss the many new features that were added with SystemVerilog. With that said, many SystemVerilog features are endorsed by numerous projects and designers, as evidenced by the abundance of style guides [appx] that act as a current but unofficial documentation of SystemVerilog's synthesizable features. The SystemVerilog IEEE 1800 specification also describes many elements that are not consistently synthesizable, such as classes, hierarchical references, interfaces, and dynamic arrays \cite{1800-2017, sutherland}. This may be due to poor tool-support for a feature, or that the feature is similar to a prohibited feature in the IEEE 1364.1 standard. For example, \autoref{fig:dc_vs_synplify} shows differences in synthesis support between two Synopsys synthesis tools.
+RTL engineers use C-like constructs [gloss] such as procedural blocks, \mintinline{systemverilog}{for} loops, and \mintinline{systemverilog}{if} statements from Verilog; and \mintinline{systemverilog}{struct}, \mintinline{systemverilog}{union}, and \mintinline{systemverilog}{enum} constructs from SystemVerilog. To promote uniformity among tools, IEEE standardized synthesis of Verilog 1364 features under the label ``1364.1". However, there has been no official ``1800.1" SystemVerilog synthesis standard to discuss the many new features that were added with SystemVerilog. With that said, many SystemVerilog features are endorsed by numerous projects and designers, as evidenced by the abundance of style guides [appx] that act as a current but unofficial documentation of SystemVerilog's synthesizable features. The SystemVerilog IEEE 1800 specification also describes many elements that are not consistently synthesizable, such as classes, hierarchical references, interfaces, and dynamic arrays \cite{1800-2017, sutherland}. This may be due to inconsistent tool-support for a feature \cite{svtests}, or that the feature is similar to a prohibited feature in the IEEE 1364.1 standard. For example, \autoref{fig:dc_vs_synplify} shows differences in synthesis support between two Synopsys synthesis tools.
 
 \FloatBarrier
 

tex/chapters/8_other_classes.tex

@@ -6,12 +6,12 @@ \chapter{Potential Applications in Other Classes}
 
 \section{``Verification with UVM and SVA''}
 
-Verification is an enormous aspect of chip design, so teaching students the principles of Universal Verification Methodology (UVM) and SystemVerilog Assertions (SVA) can be of paramount value in industry preparation. Courses like North Carolina State University's ECE 748: ``Advanced Verification with UVM'' have seen large popularity as companies are in constant demand for well-trained verification engineers. As of 9/17/23, Verilator has limited support for UVM and SVA, but is getting closer to full support every day [ref:video,issue]. If complete support is required, the open-source build-manager FuseSoC can still provide an accessible CLI for proprietary tools, lowering the learning curve. Additionally, adopting a comprehensive Design Verification (DV) style guide can ensure that students continue following best practices when working on verification tasks. Notably, lowRISC has a popular and thorough UVM and SystemVerilog DV feature style-guide. [ref]
+Verification is an enormous aspect of chip design, so teaching students the principles of Universal Verification Methodology (UVM) and SystemVerilog Assertions (SVA) can be of paramount value in industry preparation. Courses like North Carolina State University's ECE 748: ``Advanced Verification with UVM'' have seen large popularity as companies are in constant demand for well-trained verification engineers. As of 9/17/23, Verilator has limited support for UVM and SVA, but is getting closer to full support every day \cite{VerilatorUVM, BieganskiORConf, VerilatorSVA}. If complete support is required, the open-source build-manager FuseSoC can still provide an accessible CLI for proprietary tools, lowering the learning curve. Additionally, adopting a comprehensive Design Verification (DV) style guide can ensure that students continue following best practices when working on verification tasks. Notably, lowRISC has a popular and thorough UVM and SystemVerilog DV feature style-guide \cite{lowRISCstyleguides}.
 
 \section{``Embedded Systems and SoC Design''}
 
-Embedded systems and SoC design courses can leverage a plethora of open-source, high-speed IP blocks that are commonly used in FPGA designs. There are many popular open-source designs for HDMI [ref], DVI [ref], Ethernet [ref], PCIe [ref], and AXI [ref]. An educator could provide a similar experience to my ``Labs with CVA6'' project by teaching students the inner workings of advanced serial communication modules. Proficiency in high-speed interfaces is highly sought after in industry positions.
+Embedded systems and SoC design courses can leverage a plethora of open-source, high-speed IP blocks that are commonly used in FPGA designs. There are many popular open-source designs for HDMI \cite{hdlutilhdmiGitHub, projfdisplaycontrollerGitHub, cliffordwolfSimpleVOutGitHub}, Ethernet \cite{alexforencichverilogethernetGitHub}, PCIe \cite{alexforencichverilogpcieGitHub, enjoydigitallitepcieGitHub}, and AXI \cite{pulpplatformaxiGitHub, alexforencichverilogaxiGitHub}. An educator could provide a similar experience to my ``Labs with CVA6'' project by teaching students the inner workings of advanced serial communication modules. Proficiency in high-speed interfaces is highly sought after in industry positions.
 
 \section{``ASIC and VLSI Projects''}
 
-For courses focusing on Application-Specific Integrated Circuits (ASICs), open-source resources become critical. Licensing and signing Non-Disclosure Agreements (NDAs) for proprietary PDKs are often impractical or time-consuming for instructors, limiting course opportunities. Fortunately, initiatives like the OpenROAD Project and the SkyWater PDK (SKY130) offer students access to fully-featured ASIC flows. For example, UC Berkeley's EE 194: ``The Tapeout Class'' utilized Hammer and OpenROAD to offer students the opportunity to tape out an SoC in a semester. Moreover, affordable SKY130 fabrication opportunities like Tinytapeout (\SI{160}{\micro\metre} \texttimes \SI{100}{\micro\metre} for \$100) and Google MPW lottery (\SI{2920}{\micro\metre} \texttimes \SI{3520}{\micro\metre} for free) enable students to take their designs from simulation to real-world fabrication, providing a hands-on experience that reinforces their understanding of the ASIC design process.
+For courses focusing on Application-Specific Integrated Circuits (ASICs), open-source resources become critical. Licensing and signing Non-Disclosure Agreements (NDAs) for proprietary PDKs are often impractical or time-consuming for instructors, limiting course opportunities. Fortunately, initiatives like the OpenROAD Project and the SkyWater PDK (SKY130) offer students access to fully-featured ASIC flows. For example, UC Berkeley's EE 194: ``The Tapeout Class'' utilized Hammer and OpenROAD to offer students the opportunity to tape out an SoC in a semester \cite{ZhaoLatchUp}. Moreover, affordable SKY130 fabrication opportunities like Tinytapeout (\SI{160}{\micro\metre} \texttimes \SI{100}{\micro\metre} for \$100 \cite{tinytapeoutTinyTapeout}) and Google MPW lottery (\SI{2920}{\micro\metre} \texttimes \SI{3520}{\micro\metre} for free \cite{efablessCaravel}) enable students to take their designs from simulation to real-world fabrication, providing a hands-on experience that reinforces their understanding of the ASIC design process.