added sutherland textbook as resource

tex/chapters/3_digital_design.tex

@@ -56,7 +56,7 @@ \section{Teaching features that rely on inference is difficult but important.}
 
 To promote uniformity among tools, IEEE standardized synthesis of Verilog 1364 features under the label \enquote{1364.1}.
 However, there has been no official \enquote{1800.1} SystemVerilog synthesis standard to discuss the many new features that were added with SystemVerilog.
-Many SystemVerilog IEEE 1800 features are not consistently synthesizable by popular synthesis tools, such as classes, interfaces, and dynamic arrays \cite{1800-2017, sutherland}.
+Many SystemVerilog IEEE 1800 features are not consistently synthesizable by popular synthesis tools, such as classes, interfaces, and dynamic arrays \cite{1800-2017, sutherland, sutherland:book}.
 This may result from a SystemVerilog feature being subjectively similar to a prohibited feature in the IEEE 1364.1 standard, or may be due to insufficient tool development time.
 For these reasons, support for many features is inconsistent across different open-source tools \cite{svtests}, and \autoref{fig:dc_vs_synplify} shows Synopsys' own tools have inconsistencies across each-other.
 Since there is no official synthesis standard, style guides and linters have filled the role of unofficial documentation of SystemVerilog's synthesizable features to help engineers navigate the inconsistencies across different tools.

tex/chapters/4_resources.tex

@@ -8,12 +8,12 @@ \chapter{Best Resources for Learning Synthesizable SystemVerilog}
 
 \section{Stuart Sutherland's synthesis guide is most valuable.}
 
-\enquote{Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification} by Stuart Sutherland and Don Mills acts as a comprehensive list of synthesizable SystemVerilog features.
-Despite the absence of an official SystemVerilog synthesis standard, this paper gives valuable insight into synthesizable language features, emphasizing their practical application into modern hardware designs.
+\enquote{Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification} by Stuart Sutherland and Don Mills \cite{sutherland} and \enquote{RTL Modeling with SystemVerilog For Simulation and Synthesis} by Stuart Sutherland \cite{sutherland:book} act as a comprehensive record of synthesizable SystemVerilog features.
+Despite the absence of an official SystemVerilog synthesis standard, this paper and textbook give valuable insight into synthesizable language features, emphasizing their practical application in modern hardware designs.
 Sutherland and Mills surveyed the Synopsys tools, Design Compiler and Synplify-Pro, to trace the evolution of Verilog-1984 though SystemVerilog-2009 as a comprehensive hardware design and verification language.
 To assist those working on \enquote{Labs with CVA6}, I composed and included a summary of Sutherland's synthesis guide \cite{labsWithCVA6}.
 Since then, I have shared this summary with dozens of students looking to improve their understanding of synthesizable Verilog.
-Sutherland's guide (or my summary) should be provided to students to ensure a strong introduction to synthesizable Verilog syntax and best practices.
+Stuart Sutherland's guides (or my summary) should be provided to students to ensure a strong introduction to synthesizable Verilog syntax and best practices.
 
 \section{Style guides and linters record synthesizable features and best practices.}
 \label{section:style_guides}

tex/thesis.bib

@@ -8,6 +8,14 @@ @misc{sutherland
   year = {2013}
 }
 
+@book{sutherland:book,
+  author = {Sutherland, Stuart},
+  title = {{R}{T}{L} {M}odeling with {S}ystem{V}erilog {F}or {S}imulation and {S}ynthesis},
+  publisher = {Sutherland HDL, Inc},
+  isbn = {9781546776345},
+  year = {2017}
+}
+
 @misc{mckinsey,
   author = {Badlam, Justin and Clark, Stephen and Gajendragadkar, Suhrid and Kumar, Adi and O'Rourke, Sara and Swartz, Dale},
   title = {{T}he {C}{H}{I}{P}{S} and {S}cience {A}ct: {H}ere's what's in it},