chapter 3

.github/workflows/code.yml

@@ -0,0 +1,39 @@
+name: Test Code Examples
+
+on: [push]
+
+jobs:
+  Verify-Solution:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - name: Set up Python 3.x
+        uses: actions/setup-python@v4
+        with:
+          python-version: '3.x'
+      - name: Download FuseSoC
+        run: |
+          python -m pip install --upgrade pip
+          pip install fusesoc
+          fusesoc --version
+      - name: Install gcc-10
+        run: |
+          sudo apt update
+          sudo apt install -y build-essential
+          sudo apt install -y gcc-10 g++-10 cpp-10
+          sudo update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-10 100 --slave /usr/bin/g++ g++ /usr/bin/g++-10 --slave /usr/bin/gcov gcov /usr/bin/gcov-10
+          gcc --version
+      - name: Download OSS
+        run: |
+          curl -JOL https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2023-05-23/oss-cad-suite-linux-x64-20230523.tgz
+          tar -xzvf oss-cad-suite-linux-x64-20230523.tgz -C ./
+          rm -rf oss-cad-suite-linux-x64-20230523.tgz
+          echo "$GITHUB_WORKSPACE/oss-cad-suite/bin" >> $GITHUB_PATH
+      - name: Test C-like
+        run: |
+          cd $GITHUB_WORKSPACE/code/c-like
+          make
+      - name: Test Cache Lab
+        run: |
+          cd $GITHUB_WORKSPACE/code/cache_lab
+          make

code/c-like/Makefile

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+
+all: clean verilator
+
+obj_dir/Vtb: tb.sv high.svh low.svh
+	verilator tb.sv --binary -Wall -Wno-fatal --top tb
+verilator: obj_dir/Vtb
+	./obj_dir/Vtb
+
+clean:
+	rm -rf obj_dir Vtb.vvp build

code/c-like/high.svh

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+
+function automatic logic [4:0] find_first_set32(logic [31:0] in);
+    logic [4:0] out = 0;
+    for (integer i = 1; i < 32; i++)
+        if (in[i])
+            out = i;
+    return out;
+endfunction
+
+assign out = find_first_set32(in);

code/c-like/low.svh

@@ -0,0 +1,18 @@
+
+assign out =
+    in[31] ? 31 : in[30] ? 30 :
+    in[29] ? 29 : in[28] ? 28 :
+    in[27] ? 27 : in[26] ? 26 :
+    in[25] ? 25 : in[24] ? 24 :
+    in[23] ? 23 : in[22] ? 22 :
+    in[21] ? 21 : in[20] ? 20 :
+    in[19] ? 19 : in[18] ? 18 :
+    in[17] ? 17 : in[16] ? 16 :
+    in[15] ? 15 : in[14] ? 14 :
+    in[13] ? 13 : in[12] ? 12 :
+    in[11] ? 11 : in[10] ? 10 :
+    in[ 9] ?  9 : in[ 8] ?  8 :
+    in[ 7] ?  7 : in[ 6] ?  6 :
+    in[ 5] ?  5 : in[ 4] ?  4 :
+    in[ 3] ?  3 : in[ 2] ?  2 :
+    in[ 1] ?  1 : 0;

code/c-like/tb.sv

@@ -0,0 +1,48 @@
+module find_first_set32 #(
+    parameter string IMPLEMENTATION
+) (
+    input   logic [31:0]    in,
+    output  logic [4:0]     out
+);
+
+if (IMPLEMENTATION == "LOW") begin : low
+    `include "low.svh"
+end else if (IMPLEMENTATION == "HIGH") begin : high
+    `include "high.svh"
+end else begin : bad
+    initial begin
+        $error("Expected valid values for IMPLEMENTATION are \"LOW\" or \"HIGH\". Received \"%s\".", IMPLEMENTATION);
+        $finish;
+    end
+end
+
+endmodule
+
+module tb;
+
+logic clk = 0;
+always #1 clk <= ~clk;
+
+logic [31:0] value;
+
+find_first_set32 #(.IMPLEMENTATION("LOW")) l (.in(value));
+find_first_set32 #(.IMPLEMENTATION("HIGH")) h (.in(value));
+
+always @(negedge clk) begin
+    if (l.out !== h.out) begin
+        $error("Not equivalent for in=%0h: l=%d h=%d", value, l.out, h.out);
+        $finish;
+    end
+end
+
+integer i;
+initial begin
+    for (i = 0; i < 100000; i++) begin
+        value = $urandom();
+        @(posedge clk);
+    end
+    $display("All equal.");
+    $finish;
+end
+
+endmodule

code/cache_lab/Makefile

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+
+all: clean verify
+
+verify: build/cache.svh
+	diff cache.svh build/cache.svh
+
+build/cache.svh:
+	mkdir -p build
+	curl -s "https://raw.githubusercontent.com/sifferman/labs-with-cva6/2b788a9511ce8e0282f4ee5a8cbae2135eb0c540/labs/caching/part2/starter/ucsbece154b_victim_cache.sv" | sed -n "148,168p" > $@
+
+clean:
+	rm -rf build

code/cache_lab/cache.svh

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+//                  DLL Structure                   //
+// MRU - ... - way.mru - way - way.lru - ... -  LRU //
+
+typedef logic [$clog2(NR_ENTRIES)-1:0] way_index_t;
+
+struct packed {
+    logic [TAG_SIZE-1:0] tag;
+    way_index_t lru; // less recently used
+    way_index_t mru; // more recently used
+    logic valid;
+} dll_d[NR_ENTRIES], dll_q[NR_ENTRIES];
+
+// lru register
+way_index_t lru_d, lru_q, mru_d, mru_q;
+
+// index to bump
+way_index_t read_index, write_index;
+
+
+// separate the data from the dll help with optimization
+logic [LINE_WIDTH-1:0] data_d[NR_ENTRIES], data_q[NR_ENTRIES];

code/digitaljs_online.sv

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+module piso #(
+  parameter [7:0] DATA_WIDTH = 16
+) (
+  input   logic                   clk,
+  input   logic                   rst_n,
+  input   logic                   load_i,
+  input   logic [DATA_WIDTH-1:0]  loaddata_i,
+  output  logic                   serial_o
+);
+
+logic [DATA_WIDTH-1:0] data_d, data_q;
+
+always_comb begin
+  if (load_i)
+    data_d = loaddata_i;
+  else
+    data_d = (data_q >> 1);
+end
+
+always_ff @(posedge clk or negedge rst_n) begin
+  if (!rst_n) begin
+    data_q <= '0;
+  end else begin
+    data_q <= data_d;
+  end
+end
+
+assign serial_o = data_q[0];
+
+endmodule

code/opt.svh

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+wire [2:0] a;
+always_comb begin
+  out = 0;
+  for (integer i = 0; i < 3; i++)
+    if (a[i])
+      out = 1;
+end

figures/c-like.tex

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+
+\begin{figure}[t]
+    \centering
+
+    \subfloat[
+        Using purely structural constructs to create MUXes can provide long and superfluous code.
+    ]{
+        \begin{minipage}{0.8\textwidth}
+            \footnotesize
+            \inputminted[frame=single]{systemverilog}{code/c-like/low.svh}
+        \end{minipage}
+    }
+
+    \subfloat[
+        Using C-like constructs such as a \mintinline{systemverilog}{function}, \mintinline{systemverilog}{if} statement, and \mintinline{systemverilog}{for} loop can provide much cleaner code.
+    ]{
+        \begin{minipage}{0.8\textwidth}
+            \footnotesize
+            \inputminted[frame=single]{systemverilog}{code/c-like/high.svh}
+        \end{minipage}
+    }
+
+    \caption{Comparison of purely structural Verilog versus C-like Verilog. To demonstrate this comparison, provided are two different implementations of the Find First Set operation.}
+    \label{fig:c-like}
+
+\end{figure}

figures/cache_lab.tex

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+
+\begin{figure}[t]
+    \centering
+    \inputminted[frame=single]{systemverilog}{code/cache_lab/cache.svh}
+    \caption{Snippet of ``Labs with CVA6'' cache lab starter code \cite{labsWithCVA6}}
+    \label{fig:cache_lab}
+\end{figure}

figures/dc_vs_synplify.tex

@@ -2,6 +2,6 @@
 \begin{figure}[t]
     \centering
     \frame{\includegraphics[width=\linewidth]{figures/dc_vs_synplify.pdf}}
-    \caption{Differences in SystemVerilog Support in DC vs. Synplify-Pro from ``Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification''\cite{sutherland}}
+    \caption{Differences in SystemVerilog Support in DC vs. Synplify-Pro from ``Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification'' \cite{sutherland}}
     \label{fig:dc_vs_synplify}
 \end{figure}

figures/digitaljs_online.tex

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+
+\begin{figure}[t]
+    \centering
+    \includegraphics[width=\linewidth]{figures/digitaljs_online.pdf}
+    \caption{Schematic for a Parallel-in Serial-out shift register generated by the netlist graph viewer DigitalJS Online \cite{DigitalJSOnline}}
+    \label{fig:digitaljs_online}
+\end{figure}

figures/opt.tex

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+
+\begin{figure}[t]
+    \centering
+
+    \subfloat[
+        If any bits of \mintinline{systemverilog}{a} are set, then \mintinline{systemverilog}{out} is \mintinline{systemverilog}{1}.
+    ]{
+        \begin{minipage}{0.8\textwidth}
+            \inputminted[frame=single]{systemverilog}{code/opt.svh}
+        \end{minipage}
+    }
+
+    \subfloat[
+        Vivado infers the code as one parallel LUT.
+    ]{
+        \includegraphics[width=0.9\linewidth]{figures/opt/vivado.pdf}
+    }
+
+    \subfloat[
+        Yosys without optimizations enabled infers the code as a series of 2:1 MUXes.
+    ]{
+        \includegraphics[width=0.7\linewidth]{figures/opt/yosys_noopt.pdf}
+    }
+
+    \subfloat[
+        Yosys with optimizations enabled infers the code as one parallel OR gate.
+    ]{
+        \includegraphics[width=0.7\linewidth]{figures/opt/yosys_opt.pdf}
+    }
+
+    \caption{Comparison of differences in synthesis.}
+    \label{fig:opt}
+
+\end{figure}