Fix typo in intro

tex/chapters/1_introduction.tex

@@ -20,7 +20,7 @@ \chapter{Introduction}
 If timing cannot be met, the layout or HDL implementation may need to be adjusted.
 Finally, after the layout and simulations checks pass, the design is converted into a Graphic Data Stream (GDS) file which is sent to a semiconductor foundry for mass-production.
 
-Because of the multitude of skills are required to create an ASIC design, it is crucial for Universities to offer a strong foundation in writing and working with HDLs to design hardware.
+Because of the multitude of skills required to create an ASIC design, it is crucial for Universities to offer a strong foundation in writing and working with HDLs to design hardware.
 Nevertheless, HDLs come with a formidable learning curve, partly due to the difficulties of distinguishing between what code is synthesizable (able to be converted into hardware) and what should be used solely for verification purposes.
 Additionally, the prevalence of bugs in common HDL tools, the extraordinary inaccessibility of proprietary tools, and the lack of reliable online educational resources can be a major deterrent for students and hobbyists who wish to experiment with digital design on their own.
 Another factor contributing to the complexity is the interdisciplinary nature of ASIC design.