diff --git a/tex/chapters/2_open_source_tools.tex b/tex/chapters/2_open_source_tools.tex index 66065fb..c4dc529 100644 --- a/tex/chapters/2_open_source_tools.tex +++ b/tex/chapters/2_open_source_tools.tex @@ -14,7 +14,9 @@ \section{Open-source tools are easy to install.} \section{Unique benefits and features of open-source tools.} -Undoubtedly, proprietary tools offer a multitude of functionalities for advanced users that open-source tools cannot offer. However, open-source tools offer many unique features that are more desired by beginners. For example, Icarus runs short simulations much faster than proprietary simulators, making it perfect for receiving instant feedback as students are still learning the language syntax. Similarly, Yosys and Nextpnr perform synthesis and layout significantly faster than tools such as Vivado and Design Compiler, allowing for more rapid prototyping. Also, while ModelSim may happily parse and simulate un-synthesizable code, Verilator will give much more strict warnings, helping to demonstrate the syntax and features that should be allowed in synthesizable designs. (This is further discussed in \autoref{chapter:digital_design}.) Finally, open-source tools get updates every day, and instructors are able to report bugs and request new features. Depending on the difficulty of the request, the tool maintainers may complete the request within a few months. Multiple of my courses have directly benefited from this [appx]. Instructors may even decide they want to do a pull-request themselves; I personally have contributed two new warnings to Verilator in hopes of teaching best-practices. [appx] This is contrasted with the fact that many universities are not always running the most up-to-date proprietary software. For example, as of 9/10/23, UC Santa Barbara's Engineering Computing Infrastructure's latest version of ModelSim is 10.7d from April 2019, which does not support width-casting from parameters, which affected the UCSB Spring 2023 ECE 152A course experience. Bugs in tools will undoubtedly happen, but the only solution Siemens offers is to pay for an updated version with the bug fixed. Contrast this with submitting a GitHub issue with Verilator, and having the bug fixed by the next time the course is offered. Open-source tools are often simply the better choice for instructors. +Undoubtedly, proprietary tools offer a multitude of functionalities for advanced users that open-source tools cannot offer. However, open-source tools offer many unique features that are more desired by beginners. For example, Icarus runs short simulations much faster than proprietary simulators, making it perfect for receiving instant feedback as students are still learning the language syntax. Similarly, Yosys and Nextpnr perform synthesis and layout significantly faster than tools such as Vivado and Design Compiler, allowing for more rapid prototyping. Also, while ModelSim may happily parse and simulate un-synthesizable code, Verilator will give much more strict warnings, helping to demonstrate the syntax and features that should be allowed in synthesizable designs. (This is further discussed in \autoref{chapter:digital_design}.) + +Possibly the most important attribute of open-source tools is that they get updates every day, and instructors have full transparency when reporting bugs and requesting new features. Depending on the difficulty of the request, the tool maintainers may complete the request within a few months. Multiple of my courses have directly benefited from this [appx]. Instructors may even decide they want to do a pull-request themselves; I personally have contributed two new warnings to Verilator in hopes of teaching best-practices. [appx] This is contrasted with the fact that many universities are not always running the most up-to-date proprietary software. For example, as of 9/10/23, UC Santa Barbara's Engineering Computing Infrastructure's latest version of ModelSim is 10.7d from April 2019, which does not support width-casting from parameters, which affected the UCSB Spring 2023 ECE 152A course experience. Bugs in tools will undoubtedly happen, but the only solution Siemens offers is to pay for an updated version with the bug fixed. Contrast this with submitting a GitHub issue with Verilator, and having the bug fixed by the next time the course is offered. Open-source tools are often simply the better choice for instructors. \section{Avoid graphical user interfaces.} diff --git a/tex/chapters/4_resources.tex b/tex/chapters/4_resources.tex index 41b6705..c4474e2 100644 --- a/tex/chapters/4_resources.tex +++ b/tex/chapters/4_resources.tex @@ -18,8 +18,8 @@ \section{Verilog tutorial websites should be treated cautiously.} It is important to stress the importance of following the provided style guides for Verilog syntax over some of the most popular Verilog tutorial websites, such as ASIC World, Chipverify, and Nandland. Despite the user-friendly approach adopted by these websites, which mirror renowned programming tutorial platforms such as GeekforGeeks, Verilog tutorial websites often propagate misguided advice for novice hardware developers. While style-guides can act as a reference to well-verified practices for beginners and professionals alike, tutorial websites do not always teach current-day, synthesizable design syntax that is compatible with a multitude of tools. Only if students maintain adherence to the instructor-specified style-guides and the subset of synthesizable features, then tutorial websites can be used as resources. -\input{figures/asicworld} \input{figures/always_ff} +\input{figures/asicworld} For example, while a TA for ECE 152A, 154A, and 154B, the most prevalent misinformation they encouraged in students was to put combinational logic inside of \mintinline{systemverilog}{always_ff} blocks. (See \autoref{fig:asicworld}). The lowRISC Style Guide, the BSG SystemVerilog Coding Standards, and the IEEE 1364.1-2005 Verilog Synthesis Standard all recommend only putting resets, sets, and enables in \mintinline{systemverilog}{always_ff} blocks \cite{lowRISCstyleguides, BSGstyleguide, 1364.1-2005}. Unnecessarily large \mintinline{systemverilog}{always_ff} blocks are prone to bugs because \mintinline{systemverilog}{always_ff} blocks don't offer warnings on unhandled code paths, blocking and nonblocking-assignment mismatches can lead to undefined behavior, and synthesis tools may incorrectly infer the incorrect type of flip-flop. (See \autoref{fig:always_ff}) In my experience teaching SystemVerilog, whenever a student asked for help solving a bug, but followed this design practice, I immediately asked them to separate the block into an \mintinline{systemverilog}{always_comb} and \mintinline{systemverilog}{always_ff}. Over half the time, that simple refactor incidentally fixed the student's bug. diff --git a/tex/thesis.bib b/tex/thesis.bib index b0e2ae0..4f5b356 100644 --- a/tex/thesis.bib +++ b/tex/thesis.bib @@ -9,103 +9,103 @@ @misc{sutherland } @misc{mckinsey, - author = {Badlam, Justin and Clark, Stephen and Gajendragadkar, Suhrid and Kumar, Adi and O'Rourke, Sara and Swartz, Dale}, - title = {{T}he {C}{H}{I}{P}{S} and {S}cience {A}ct: {H}ere's what's in it}, - howpublished = {\url{https://www.mckinsey.com/industries/public-sector/our-insights/the-chips-and-science-act-heres-whats-in-it}}, + author = {Badlam, Justin and Clark, Stephen and Gajendragadkar, Suhrid and Kumar, Adi and O'Rourke, Sara and Swartz, Dale}, + title = {{T}he {C}{H}{I}{P}{S} and {S}cience {A}ct: {H}ere's what's in it}, + howpublished = {\url{https://www.mckinsey.com/industries/public-sector/our-insights/the-chips-and-science-act-heres-whats-in-it}}, month = {October}, - year = {2022}, - note = {[Accessed 18-09-2023]}, + year = {2022}, + note = {[Accessed 18-09-2023]}, } @misc{taipeitimes, - author = {Wang, Lisa}, - title = {{T}{S}{M}{C} says three fabs to start production in 2024}, - howpublished = {\url{https://www.taipeitimes.com/News/biz/archives/2022/08/31/2003784445}}, + author = {Wang, Lisa}, + title = {{T}{S}{M}{C} says three fabs to start production in 2024}, + howpublished = {\url{https://www.taipeitimes.com/News/biz/archives/2022/08/31/2003784445}}, month = {August}, - year = {2022}, - note = {[Accessed 18-09-2023]}, + year = {2022}, + note = {[Accessed 18-09-2023]}, } @misc{GooglePartnersWithSkyWater, - author = {rocket55}, - title = {{G}oogle {P}artners with {S}ky{W}ater and {E}fabless to {E}nable {O}pen {S}ource {M}anufacturing of {C}ustom {A}{S}{I}{C}s - {S}kywater {T}echnology --- skywatertechnology.com}, - howpublished = {\url{https://www.skywatertechnology.com/google-partners-with-skywater-and-efabless-to-enable-open-source-manufacturing-of-custom-asics/}}, + author = {rocket55}, + title = {{G}oogle {P}artners with {S}ky{W}ater and {E}fabless to {E}nable {O}pen {S}ource {M}anufacturing of {C}ustom {A}{S}{I}{C}s - {S}kywater {T}echnology --- skywatertechnology.com}, + howpublished = {\url{https://www.skywatertechnology.com/google-partners-with-skywater-and-efabless-to-enable-open-source-manufacturing-of-custom-asics/}}, month = {November}, - year = {2020}, - note = {[Accessed 18-09-2023]}, + year = {2020}, + note = {[Accessed 18-09-2023]}, } @misc{googleSilicon, - author = {{Google for Developers}}, - title = {{B}uild your own silicon}, - howpublished = {\url{https://developers.google.com/silicon}}, - note = {[Accessed 18-09-2023]}, + author = {{Google for Developers}}, + title = {{B}uild your own silicon}, + howpublished = {\url{https://developers.google.com/silicon}}, + note = {[Accessed 18-09-2023]}, } @misc{kynixDesignFlow, - author = {Kynix}, - title = {{D}etailed {E}xplanation of {C}hip {D}esign {F}low}, - howpublished = {\url{https://www.kynix.com/Blog/Detailed-Explanation-of-Chip-Design-Flow.html}}, + author = {Kynix}, + title = {{D}etailed {E}xplanation of {C}hip {D}esign {F}low}, + howpublished = {\url{https://www.kynix.com/Blog/Detailed-Explanation-of-Chip-Design-Flow.html}}, month = {December}, - year = {2017}, - note = {[Accessed 18-09-2023]}, + year = {2017}, + note = {[Accessed 18-09-2023]}, } @misc{intelDesignFlow, - author = {Intel}, - title = {Intel\textsuperscript{\textregistered} Stratix\textsuperscript{\textregistered} 10 Device Design Guidelines}, - howpublished = {\url{https://www.intel.com/content/www/us/en/docs/programmable/683738/current/design-flow.html}}, + author = {Intel}, + title = {Intel\textsuperscript{\textregistered} Stratix\textsuperscript{\textregistered} 10 Device Design Guidelines}, + howpublished = {\url{https://www.intel.com/content/www/us/en/docs/programmable/683738/current/design-flow.html}}, month = {August}, - year = {2022}, - note = {[Accessed 18-09-2023]}, + year = {2022}, + note = {[Accessed 18-09-2023]}, } @misc{anysiliconDesignFlow, - author = {anysilicon}, - title = {{A}{S}{I}{C} {D}esign {F}low -- {T}he {U}ltimate {G}uide}, - howpublished = {\url{https://anysilicon.com/asic-design-flow-ultimate-guide/}}, - note = {[Accessed 18-09-2023]}, + author = {anysilicon}, + title = {{A}{S}{I}{C} {D}esign {F}low -- {T}he {U}ltimate {G}uide}, + howpublished = {\url{https://anysilicon.com/asic-design-flow-ultimate-guide/}}, + note = {[Accessed 18-09-2023]}, } @misc{icarusGitHub, - author = {Stephen Williams}, - title = {steveicarus/iverilog: {I}carus {V}erilog}, - howpublished = {\url{https://github.com/steveicarus/iverilog}}, - note = {[Accessed 18-09-2023]}, + author = {Stephen Williams}, + title = {steveicarus/iverilog: {I}carus {V}erilog}, + howpublished = {\url{https://github.com/steveicarus/iverilog}}, + note = {[Accessed 18-09-2023]}, } @misc{verilatorGitHub, - author = {Wilson Snyder}, - title = {verilator/verilator: {V}erilator open-source {S}ystem{V}erilog simulator and lint system}, - howpublished = {\url{https://github.com/verilator/verilator}}, - note = {[Accessed 18-09-2023]}, + author = {Wilson Snyder}, + title = {verilator/verilator: {V}erilator open-source {S}ystem{V}erilog simulator and lint system}, + howpublished = {\url{https://github.com/verilator/verilator}}, + note = {[Accessed 18-09-2023]}, } @misc{gtkwaveGitHub, - author = {Ralf Fuest}, - title = {gtkwave/gtkwave: {G}{T}{K}{W}ave is a fully featured {G}{T}{K}+ based wave viewer for {U}nix and {W}in32 which reads {L}{X}{T}, {L}{X}{T}2, {V}{Z}{T}, {F}{S}{T}, and {G}{H}{W} files as well as standard {V}erilog {V}{C}{D}/{E}{V}{C}{D} files}, - howpublished = {\url{https://github.com/gtkwave/gtkwave}}, - note = {[Accessed 18-09-2023]}, + author = {Ralf Fuest}, + title = {gtkwave/gtkwave: {G}{T}{K}{W}ave is a fully featured {G}{T}{K}+ based wave viewer for {U}nix and {W}in32 which reads {L}{X}{T}, {L}{X}{T}2, {V}{Z}{T}, {F}{S}{T}, and {G}{H}{W} files as well as standard {V}erilog {V}{C}{D}/{E}{V}{C}{D} files}, + howpublished = {\url{https://github.com/gtkwave/gtkwave}}, + note = {[Accessed 18-09-2023]}, } @misc{yosysGitHub, - author = {{Y}osys{H}{Q}}, - title = {{Y}osys {O}pen {S}{Y}nthesis {S}uite}, - howpublished = {\url{https://github.com/YosysHQ/yosys}}, - note = {[Accessed 18-09-2023]}, + author = {{Y}osys{H}{Q}}, + title = {{Y}osys {O}pen {S}{Y}nthesis {S}uite}, + howpublished = {\url{https://github.com/YosysHQ/yosys}}, + note = {[Accessed 18-09-2023]}, } @misc{nextpnrGitHub, - author = {{Y}osys{H}{Q}}, - title = {nextpnr portable {F}{P}{G}{A} place and route tool}, - howpublished = {\url{https://github.com/YosysHQ/nextpnr}}, - note = {[Accessed 18-09-2023]}, + author = {{Y}osys{H}{Q}}, + title = {nextpnr portable {F}{P}{G}{A} place and route tool}, + howpublished = {\url{https://github.com/YosysHQ/nextpnr}}, + note = {[Accessed 18-09-2023]}, } @misc{vtrGitHub, - title = {verilog-to-routing/vtr-verilog-to-routing: {V}erilog to {R}outing -- {O}pen {S}ource {C}{A}{D} {F}low for {F}{P}{G}{A} {R}esearch}, - howpublished = {\url{https://github.com/verilog-to-routing/vtr-verilog-to-routing}}, - note = {[Accessed 18-09-2023]}, + title = {verilog-to-routing/vtr-verilog-to-routing: {V}erilog to {R}outing -- {O}pen {S}ource {C}{A}{D} {F}low for {F}{P}{G}{A} {R}esearch}, + howpublished = {\url{https://github.com/verilog-to-routing/vtr-verilog-to-routing}}, + note = {[Accessed 18-09-2023]}, } @inproceedings{OpenLaneGitHub, @@ -114,42 +114,42 @@ @inproceedings{OpenLaneGitHub title = {Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper}, year = {2020}, pages = {1-6}, - note = {\url{https://github.com/The-OpenROAD-Project/OpenLane}}, + note = {\url{https://github.com/The-OpenROAD-Project/OpenLane}}, } @misc{fusesocGitHub, - author = {Olof Kindgren}, - title = {olofk/fusesoc: {P}ackage manager and build abstraction tool for {F}{P}{G}{A}/{A}{S}{I}{C} development}, - howpublished = {\url{https://github.com/olofk/fusesoc}}, - note = {[Accessed 18-09-2023]}, + author = {Olof Kindgren}, + title = {olofk/fusesoc: {P}ackage manager and build abstraction tool for {F}{P}{G}{A}/{A}{S}{I}{C} development}, + howpublished = {\url{https://github.com/olofk/fusesoc}}, + note = {[Accessed 18-09-2023]}, } @misc{edalizeGitHub, - author = {Olof Kindgren}, - title = {olofk/edalize: {A}n abstraction library for interfacing {E}{D}{A} tools}, - howpublished = {\url{https://github.com/olofk/edalize}}, - note = {[Accessed 18-09-2023]}, + author = {Olof Kindgren}, + title = {olofk/edalize: {A}n abstraction library for interfacing {E}{D}{A} tools}, + howpublished = {\url{https://github.com/olofk/edalize}}, + note = {[Accessed 18-09-2023]}, } @misc{zachjssv2vGitHub, - author = {Zachary Snow}, - title = {zachjs/sv2v: {S}ystem{V}erilog to {V}erilog conversion}, - howpublished = {\url{https://github.com/zachjs/sv2v}}, - note = {[Accessed 19-09-2023]}, + author = {Zachary Snow}, + title = {zachjs/sv2v: {S}ystem{V}erilog to {V}erilog conversion}, + howpublished = {\url{https://github.com/zachjs/sv2v}}, + note = {[Accessed 19-09-2023]}, } @misc{cva6, - author = {OpenHW Group}, - title = {openhwgroup/cva6: {T}he {C}{O}{R}{E}-{V} {C}{V}{A}6 is an {A}pplication class 6-stage {R}{I}{S}{C}-{V} {C}{P}{U} capable of booting {L}inux}, - howpublished = {\url{https://github.com/openhwgroup/cva6}}, - note = {[Accessed 19-09-2023]}, + author = {OpenHW Group}, + title = {openhwgroup/cva6: {T}he {C}{O}{R}{E}-{V} {C}{V}{A}6 is an {A}pplication class 6-stage {R}{I}{S}{C}-{V} {C}{P}{U} capable of booting {L}inux}, + howpublished = {\url{https://github.com/openhwgroup/cva6}}, + note = {[Accessed 19-09-2023]}, } @misc{awesomeOpenSourceHardware, - author = {Andreas Olofsson}, - title = {aolofsson/awesome-opensource-hardware: {L}ist of awesome open source hardware tools, generators, and reusable designs}, - howpublished = {\url{https://github.com/aolofsson/awesome-opensource-hardware}}, - note = {[Accessed 18-09-2023]}, + author = {Andreas Olofsson}, + title = {aolofsson/awesome-opensource-hardware: {L}ist of awesome open source hardware tools, generators, and reusable designs}, + howpublished = {\url{https://github.com/aolofsson/awesome-opensource-hardware}}, + note = {[Accessed 18-09-2023]}, } @misc{olofssonLatchUp, @@ -162,18 +162,18 @@ @misc{olofssonLatchUp @misc{licensePricesReddit, author = {u/[deleted]}, - title = {{M}odelsim and {Q}uesta license price: {T}oo expensive?}, - howpublished = {\url{https://www.reddit.com/r/FPGA/comments/c8z1x9/modelsim_and_questa_license_price_too_expensive/}}, + title = {{M}odelsim and {Q}uesta license price: {T}oo expensive?}, + howpublished = {\url{https://www.reddit.com/r/FPGA/comments/c8z1x9/modelsim_and_questa_license_price_too_expensive/}}, month = {July}, - year = {2019}, - note = {[Accessed 18-09-2023]}, + year = {2019}, + note = {[Accessed 18-09-2023]}, } @misc{osscadsuitebuildGitHub, - author = {{Y}osys{H}{Q}}, - title = {{M}ulti-platform nightly builds of open source digital design and verification tools}, - howpublished = {\url{https://github.com/YosysHQ/oss-cad-suite-build}}, - note = {[Accessed 18-09-2023]}, + author = {{Y}osys{H}{Q}}, + title = {{M}ulti-platform nightly builds of open source digital design and verification tools}, + howpublished = {\url{https://github.com/YosysHQ/oss-cad-suite-build}}, + note = {[Accessed 18-09-2023]}, } @misc{RichmondLatchUp, @@ -203,46 +203,46 @@ @article{1364.1-2005 } @misc{DigitalJSOnline, - author = {Marek Materzok}, - title = {{D}igital{J}{S} {O}nline}, - howpublished = {\url{https://digitaljs.tilk.eu/}}, - note = {[Accessed 18-09-2023]}, + author = {Marek Materzok}, + title = {{D}igital{J}{S} {O}nline}, + howpublished = {\url{https://digitaljs.tilk.eu/}}, + note = {[Accessed 18-09-2023]}, } @misc{labsWithCVA6, - author = {Ethan Sifferman}, - title = {{L}abs with {C}{V}{A}6}, - howpublished = {\url{https://github.com/sifferman/labs-with-cva6}}, - note = {[Accessed 18-09-2023]}, + author = {Ethan Sifferman}, + title = {{L}abs with {C}{V}{A}6}, + howpublished = {\url{https://github.com/sifferman/labs-with-cva6}}, + note = {[Accessed 18-09-2023]}, } @misc{lowRISCstyleguides, - author = {lowRISC}, - title = {low{R}{I}{S}{C} {S}tyle {G}uides}, - howpublished = {\url{https://github.com/lowRISC/style-guides/tree/master}}, - note = {[Accessed 19-09-2023]}, + author = {lowRISC}, + title = {low{R}{I}{S}{C} {S}tyle {G}uides}, + howpublished = {\url{https://github.com/lowRISC/style-guides/tree/master}}, + note = {[Accessed 19-09-2023]}, } @misc{BSGstyleguide, - author = {Taylor, Michael and {The Bespoke Silicon Group}}, - title = {{B}{S}{G} {S}ystem{V}erilog {C}oding {S}tandards}, - howpublished = {\url{https://docs.google.com/document/d/1xA5XUzBtz_D6aSyIBQUwFk_kSUdckrfxa2uzGjMgmCU/}}, - note = {[Accessed 19-09-2023]}, + author = {Taylor, Michael and {The Bespoke Silicon Group}}, + title = {{B}{S}{G} {S}ystem{V}erilog {C}oding {S}tandards}, + howpublished = {\url{https://docs.google.com/document/d/1xA5XUzBtz_D6aSyIBQUwFk_kSUdckrfxa2uzGjMgmCU/}}, + note = {[Accessed 19-09-2023]}, } @misc{asicworld, - author = {Deepak Kumar Tala and {ASIC World}}, - title = {{V}erilog {E}xamples}, - howpublished = {\url{https://www.asic-world.com/examples/verilog/}}, - year = {2014}, - note = {[Accessed 19-09-2023]}, + author = {Deepak Kumar Tala and {ASIC World}}, + title = {{V}erilog {E}xamples}, + howpublished = {\url{https://www.asic-world.com/examples/verilog/}}, + year = {2014}, + note = {[Accessed 19-09-2023]}, } @misc{ChipDev, - author = {ChipDev}, - title = {{C}hip{D}ev}, - howpublished = {\url{https://chipdev.io/}}, - note = {[Accessed 19-09-2023]}, + author = {ChipDev}, + title = {{C}hip{D}ev}, + howpublished = {\url{https://chipdev.io/}}, + note = {[Accessed 19-09-2023]}, } @book{kohn:book, @@ -253,11 +253,11 @@ @book{kohn:book year = {2020} } -@article{blum:article, +@misc{blum:article, author = {Blum, Susan}, - year = {2017}, - month = {11}, title = {The significant learning benefits of getting rid of grades}, journal = {Inside Higher Ed}, - url = {https://www.insidehighered.com/advice/2017/11/14/significant-learning-benefits-getting-rid-grades-essay} + howpublished = {\url{https://www.insidehighered.com/advice/2017/11/14/significant-learning-benefits-getting-rid-grades-essay}}, + month = {November}, + year = {2017}, } diff --git a/tex/thesis.tex b/tex/thesis.tex index 623e662..ee9d58c 100644 --- a/tex/thesis.tex +++ b/tex/thesis.tex @@ -12,7 +12,7 @@ % \usepackage{xspace} % \usepackage{braket} % \usepackage{color} -% \usepackage{setspace} +\usepackage{setspace} \usepackage{titlesec} \usepackage{soul} \usepackage[outputdir=build]{minted}