chapter 5

code/ece152a_pkg.sv

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023, University of California; Santa Barbara
+ * Distribution prohibited. All rights reserved.
+ *
+ * File: taillights_pkg.sv
+ * Description: Taillights SystemVerilog package.
+ *  Includes the enum for the FSM module
+ */
+
+package taillights_pkg;
+
+typedef enum logic [2:0] {
+    S000_000,
+    S000_100,
+    S000_110,
+    S000_111,
+    S001_000,
+    S011_000,
+    S111_000,
+    S111_111
+} state_t;
+
+endpackage

figures/ece152a_pkg.tex

@@ -0,0 +1,8 @@
+
+\begin{figure}[t]
+    \centering
+    \small
+    \inputminted[frame=single]{systemverilog}{code/ece152a_pkg.sv}
+    \caption{This is a SystemVerilog package that was provided to ECE 152A students to aid in their implementation of a 1965 Ford Thunderbird taillight state-machine.}
+    \label{fig:ece152a_pkg}
+\end{figure}

tex/chapters/5_scalability.tex

@@ -2,16 +2,18 @@
 \chapter{Teaching Code Scalability and Development Practices}
 \label{chapter:scalability}
 
-Aside from ensuring that student code follows best-practices and correctly synthesizes, an equally important skill to teach students is how to efficiently work on large-scale projects. As the number of transistors on an integrated circuit has increased, the scale of Verilog designs has also drastically increased. At Intel, the SoC that my team was verifying had over 800 Verilog source files in the design. Similarly, one of the most popular RISC-V cores, CVA6, is written in nearly 17,000 lines of code. Ensuring seamless development and limiting the number of bugs within these colossal codebases requires strong project management skills. This is achieved by automatic regression, consistent coding styles, and employing version control. In more advanced Verilog courses such as Computer Architecture or SoC design, I argue that teaching code scalability is often just as important as teaching microarchitecture implementation methods.
+Aside from ensuring that student code follows best-practices and correctly synthesizes, an equally important skill to teach students is how to efficiently work on large-scale projects. As the number of transistors on an integrated circuit has increased, the scale of Verilog designs has also drastically increased. At Intel, the SoC that my team was verifying had over 500 Verilog source files in the design. Similarly, one of the most popular RISC-V cores, CVA6, is written in nearly 17,000 lines of code \cite{cva6}. Ensuring seamless development and limiting the number of bugs within these colossal codebases requires strong project management skills. This is achieved by automatic regression, consistent coding styles, and employing version control. In more advanced Verilog courses such as Computer Architecture or SoC design, I argue that teaching code scalability is often just as important as teaching microarchitecture implementation methods.
 
 \section{SystemVerilog offers many features to aid in code organization.}
 
-Features such as packages, structs, and parameters are incredibly popular in large-scale SystemVerilog projects. And although IEEE 1364 Verilog does not support packages and structs, many RTL designers have found workarounds with \mintinline{systemverilog}{`include} files and functions. [ref:lowrisc, sv2v] These features may not be required to implement hardware algorithms, but are still extremely prevalent in well-organized, large-scale Verilog designs as well as in complex hardware algorithms such as instruction decoding and serial interfaces. In ECE 152A, ECE 154A, and ECE 154B, we were sure to teach students to apply these code organization strategies. [fig]
+\input{figures/ece152a_pkg}
+
+Features such as packages, structs, and parameters are incredibly popular in large-scale SystemVerilog projects. And although IEEE 1364 Verilog does not support packages and structs, many RTL designers have found workarounds with \mintinline{systemverilog}{`include} files and functions. \cite{lowRISCstyleguides, zachjssv2vGitHub} These features may not be \emph{required} to implement hardware algorithms such as instruction decoding and serial interfaces, but are still extremely prevalent in well-organized, large-scale Verilog designs. In ECE 152A, ECE 154A, and ECE 154B, we were sure to teach students to apply these code organization strategies. See \autoref{fig:ece152a_pkg}.
 
 \section{Version control should be used in Verilog designs.}
 
 Aside from code structure, a cornerstone of modern software development is version control. Intel, numerous other companies, and most RISC-V projects extensively rely on Git and GitHub for version management. Moreover, Git submodules and subtrees provide an elegant solution for integrating IP blocks into designs seamlessly, enhancing reusability and collaboration. Plus, allowing students to post code they've written themselves to GitHub is a great way to aid them in creating an online portfolio for themselves. In ECE 154B, students practiced using Git and GitHub to explore open-source projects, collaborate with peers, add open-source cores as submodules, and more. While software might not be the core focus for some students, being able to work with it efficiently and professionally is still extremely valuable. Because of the invaluable aid Git offers in code quality, and its extreme prevalence in all software development, it is an invaluable hard-skill for all engineers.
 
 \section{SystemVerilog assertions and in-module verification are important.}
 
-The final design strategy for promoting code scalability is to promote in-module verification. Waveform viewers are incredibly powerful and useful tools, but work best when supplemented with \mintinline{systemverilog}{$display} statements that have already identified where and when a simulation error occurred. Most SystemVerilog in industry designs is full of self-verifying modules by use of SystemVerilog assertions (SVA) and Universal Verification Methodology (UVM). Note that as of 9/10/23, since there is poor SVA and UVM support in open-source tools, many open-source projects have success using \mintinline{systemverilog}{`ifdef} macros to disable UVM and SVA calls on a per-tool basis, or projects only may use a subset of the features which are supported, or the projects resort to a basic \mintinline{systemverilog}{always} blocks instead. [fig] But no matter the specific implementation, in-module verification is a valuable design practice to teach students. In ECE 154A, ECE 154B, and ECE 152A, students were often required to design modules that incorporated simulation-only logic to test basic functionality. By adopting these universal standards, Verilog education becomes better aligned with real-world methodologies for enhanced scalability and proficiency.
+The final design strategy for promoting code scalability is to promote in-module verification. Waveform viewers are incredibly powerful and useful tools, but work best when supplemented with \mintinline{systemverilog}{$display} statements that have already identified where and when a simulation error occurred. Most SystemVerilog in industry designs is full of self-verifying modules by use of SystemVerilog assertions (SVA) and Universal Verification Methodology (UVM). Note that as of 9/10/23, since there is poor SVA and UVM support in open-source tools, projects may need to use \mintinline{systemverilog}{`ifdef} macros to disable UVM and SVA calls on a per-tool basis, may need to limit themselves to the subset of supported features, or may need to resort to a basic \mintinline{systemverilog}{always} blocks instead. But no matter the specific implementation, in-module verification is a valuable design practice to teach students. In ECE 154A, ECE 154B, and ECE 152A, students were often required to design modules that incorporated simulation-only logic to test basic functionality. By adopting these universal standards, Verilog education becomes better aligned with real-world methodologies for enhanced scalability and proficiency.

tex/thesis.bib

@@ -148,6 +148,20 @@ @misc{edalizeGitHub
 	note = {[Accessed 18-09-2023]},
 }
 
+@misc{zachjssv2vGitHub,
+	author = {Zachary Snow},
+	title = {zachjs/sv2v: {S}ystem{V}erilog to {V}erilog conversion},
+	howpublished = {\url{https://github.com/zachjs/sv2v}},
+	note = {[Accessed 19-09-2023]},
+}
+
+@misc{cva6,
+	author = {OpenHW Group},
+	title = {openhwgroup/cva6: {T}he {C}{O}{R}{E}-{V} {C}{V}{A}6 is an {A}pplication class 6-stage {R}{I}{S}{C}-{V} {C}{P}{U} capable of booting {L}inux},
+	howpublished = {\url{https://github.com/openhwgroup/cva6}},
+	note = {[Accessed 19-09-2023]},
+}
+
 @misc{awesomeOpenSourceHardware,
 	author = {Andreas Olofsson},
 	title = {aolofsson/awesome-opensource-hardware: {L}ist of awesome open source hardware tools, generators, and reusable designs},