Merge pull request #209 from sifive/arty-19.2

Make rtl target to use ram from dtim, flash from testram
sifive · Mar 20, 2019 · 318ac16 · 318ac16
2 parents 0f8c780 + ac5e78c
commit 318ac16
Show file tree

Hide file tree

Showing 14 changed files with 164 additions and 591 deletions.
diff --git a/bsp/coreip-e31-arty/metal.dhrystone.lds b/bsp/coreip-e31-arty/metal.dhrystone.lds