Instruction encoding in the comments field for metal_cache functions are incorrect

[TacoGrandeTX]

It appears that the instruction encoding in the function header blocks in cache.c are incorrect. For instance:

 * @brief CFlush.D.L1 instruction is a custom instruction implemented as a
 * state machine in L1 Data Cache (D$) with funct3=0, (for core with data caches)
 * It is an I type: .insn i opcode, func3, rd, rs1, simm12(signed immediate 12bs)
 * 31     28 27    24 23    20 19     16 15   12 11     8 7      4 3      0
 * |--------|--------|--------|--------|--------|--------|--------|--------|
 * +-------------+------------+----------+------+--------+-----------------+
 * |sign immediate12b (simm12)|   rs1    | func3|    rd  |      opcode     |
 * |-1-1-1-1 -1-1-0-0 -0-0-0-0|-x-x-x-x-x|0-0-0-|-0-0-0-0|-0-1-1-1 -0-0-1-1|
 * +--------------------------+----------+------+--------+-----------------+
 * 31     -0x40              20          15  0  12   x0  7      0x73       0

Is not matching the RISC-V Spec which shows opcode as 7 bits and rd as 5 bits:

This impacts metal_dcache_l1_flush(), metal_dcache_l1_discard() and metal_icache_l1_flush().

[bsousi5]

On Dec 17, 2019, at 8:01 AM, Ralph Fulchiero ***@***.***> wrote: It appears that the instruction encoding in the function header blocks in cache.c are incorrect. For instance: * @brief CFlush.D.L1 instruction is a custom instruction implemented as a * state machine in L1 Data Cache (D$) with funct3=0, (for core with data caches) * It is an I type: .insn i opcode, func3, rd, rs1, simm12(signed immediate 12bs) * 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 * |--------|--------|--------|--------|--------|--------|--------|--------| * +-------------+------------+----------+------+--------+-----------------+ * |sign immediate12b (simm12)| rs1 | func3| rd | opcode | * |-1-1-1-1 -1-1-0-0 -0-0-0-0|-x-x-x-x-x|0-0-0-|-0-0-0-0|-0-1-1-1 -0-0-1-1| * +--------------------------+----------+------+--------+-----------------+ * 31 -0x40 20 15 0 12 x0 7 0x73 0 Is not matching the RISC-V Spec which shows opcode as 7 bits and rd as 5 bits:

Oh you meant the comments header. Thanks will correct that.

…

<https://user-images.githubusercontent.com/38222074/71011767-a0f70700-20b3-11ea-9485-d9d5be6f82e6.png> This impacts metal_dcache_l1_flush(), metal_dcache_l1_discard() and metal_icache_l1_flush(). — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#209?email_source=notifications&email_token=AIQNVX2J2LZETQE4RUMNCMLQZDZT7A5CNFSM4J35XDSKYY3PNVWWK3TUL52HS4DFUVEXG43VMWVGG33NNVSW45C7NFSM4IBC55EQ>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AIQNVX6YJMNQSWAYRCEUBULQZDZT7ANCNFSM4J35XDSA>.