Why __metal_clic0_default_vector_handler needs to be 64 bytes aligned?

[pkarashchenko]

The __metal_clic0_default_vector_handler has 64 bytes alignment attribute.

freedom-metal/src/drivers/sifive_clic0.c

Lines 32 to 33 in 26b85c9

	void __metal_clic0_default_vector_handler(void)
	__attribute__((interrupt, aligned(64)));

it is assigned to clic->metal_mtvt_table[id] in __metal_driver_sifive_clic0_vector_register :

freedom-metal/src/drivers/sifive_clic0.c

Lines 559 to 590 in e21891c

	int __metal_driver_sifive_clic0_vector_register(
	struct metal_interrupt *controller, int id,
	metal_interrupt_vector_handler_t isr, void *priv) {
	int rc = -1;
	struct __metal_driver_sifive_clic0 *clic =
	(struct __metal_driver_sifive_clic0 *)(controller);
	// struct metal_interrupt *intc =
	// __metal_driver_sifive_clic0_interrupt_parent(controller);
	int num_subinterrupts =
	__metal_driver_sifive_clic0_num_subinterrupts(controller);
	metal_vector_mode mode = __metal_clic0_configure_get_vector_mode(clic);
	if ((mode != METAL_SELECTIVE_VECTOR_MODE) &&
	(mode != METAL_HARDWARE_VECTOR_MODE)) {
	return rc;
	}
	if ((mode == METAL_SELECTIVE_VECTOR_MODE) &&
	(__metal_clic0_interrupt_is_vectored(clic, id) == 0)) {
	return rc;
	}
	if (id < num_subinterrupts) {
	if (isr) {
	clic->metal_mtvt_table[id] = isr;
	clic->metal_exint_table[id].exint_data = priv;
	} else {
	clic->metal_mtvt_table[id] = __metal_clic0_default_vector_handler;
	clic->metal_exint_table[id].sub_int = priv;
	}
	rc = 0;
	}
	return rc;
	}

But the parameter metal_interrupt_vector_handler_t isr of __metal_driver_sifive_clic0_vector_register that is also assigned to clic->metal_mtvt_table[id] does not have 64 bytes alignment requirement.

So the question is why __metal_clic0_default_vector_handler needs to be 64 bytes aligned?

[ppmag]

Good point.
__metal_clic0_default_vector_handler is real ISR handler. CLIC specs require this handler to be 64-byte aligned (as far as I know, since it should fit into some part of the mtvec CSR).

On the other hand, isr is an arbitrary function pointer argument.
Should we add additional checks in the code to be sure isr is 64-byte aligned?

[petrokarashchenko]

Actually for vectored mode (that does not place ISR handler address into mtvec directly) I can find that vector table address placed into mtvt should be 64-byte aligned (minimum, but can increase depending on the total number of CLIC interrupts implemented). Sorry for maybe a dummy question, but could you please point me to a doc that requires all mtvt entries to be 64-byte aligned as well?

I mean that __metal_clic0_handler is a default handler for non-vectored mode and it is required to be 64-byte aligned. That is fine

freedom-metal/src/drivers/sifive_clic0.c

Lines 499 to 500 in 26b85c9

	clic->metal_mtvt_table[0] =
	(metal_interrupt_vector_handler_t)&__metal_clic0_handler;

But why __metal_clic0_default_vector_handler should be aligned as well?