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use sc_package to register python information CI #77: Pull request #41 opened by gadfort
February 20, 2024 15:49 1m 0s better-python-helper
better-python-helper
February 20, 2024 15:49 1m 0s
use sc_package to register python information CI #76: Commit 78e785a pushed by gadfort
February 20, 2024 14:49 59s better-python-helper
better-python-helper
February 20, 2024 14:49 59s
cleanup python module and test CI #75: Commit e2b4ef4 pushed by gadfort
February 16, 2024 21:16 37s fix-libs
fix-libs
February 16, 2024 21:16 37s
version 0.1.4 CI #74: Commit 0995381 pushed by gadfort
February 16, 2024 21:08 39s v0.1.4
v0.1.4
February 16, 2024 21:08 39s
v0.1.4 Wheels #8: Release v0.1.4 published by gadfort
February 16, 2024 21:08 1m 23s
February 16, 2024 21:08 1m 23s
version 0.1.4 CI #73: Commit 0995381 pushed by gadfort
February 16, 2024 21:07 39s main
main
February 16, 2024 21:07 39s
cleanup python module and test CI #72: Commit bee8985 pushed by gadfort
February 16, 2024 16:53 34s fix-libs
fix-libs
February 16, 2024 16:53 34s
Merge pull request #40 from siliconcompiler/format-verilog CI #71: Commit d8505fd pushed by gadfort
February 16, 2024 16:52 35s main
main
February 16, 2024 16:52 35s
cleanup python module and test CI #70: Commit 24b970c pushed by gadfort
February 16, 2024 14:14 43s fix-libs
fix-libs
February 16, 2024 14:14 43s
format verilog and add lint CI #69: Pull request #40 opened by gadfort
February 15, 2024 23:26 36s format-verilog
format-verilog
February 15, 2024 23:26 36s
update verible rules CI #68: Commit ecc7ce4 pushed by gadfort
February 15, 2024 23:24 35s format-verilog
format-verilog
February 15, 2024 23:24 35s
add config to verible lint CI #67: Commit 07c5895 pushed by gadfort
February 15, 2024 23:14 39s format-verilog
format-verilog
February 15, 2024 23:14 39s
disable deps CI #66: Commit b6a1c39 pushed by gadfort
February 15, 2024 22:15 34s fix-libs
fix-libs
February 15, 2024 22:15 34s
remove old python files CI #65: Commit f8b82d7 pushed by gadfort
February 15, 2024 22:13 40s fix-libs
fix-libs
February 15, 2024 22:13 40s
fix tab formatting CI #64: Commit a0ebdf0 pushed by gadfort
February 15, 2024 20:58 37s format-verilog
format-verilog
February 15, 2024 20:58 37s
fix tab formatting CI #63: Commit a040921 pushed by gadfort
February 15, 2024 20:53 36s format-verilog
format-verilog
February 15, 2024 20:53 36s
exclude SC from formatting CI #62: Commit 6510721 pushed by gadfort
February 15, 2024 20:46 37s format-verilog
format-verilog
February 15, 2024 20:46 37s
format verilog files CI #61: Commit 82ac0f8 pushed by gadfort
February 15, 2024 20:45 40s format-verilog
format-verilog
February 15, 2024 20:45 40s
setup CI flow for verilog formatting CI #60: Commit b9b1a3a pushed by gadfort
February 15, 2024 20:38 36s format-verilog
format-verilog
February 15, 2024 20:38 36s
Merge pull request #39 from siliconcompiler/fix-muxes CI #59: Commit 4e8b747 pushed by gadfort
February 15, 2024 20:12 37s main
main
February 15, 2024 20:12 37s
fix d3 selection in xmux4 CI #58: Pull request #39 opened by gadfort
February 15, 2024 20:08 35s fix-muxes
fix-muxes
February 15, 2024 20:08 35s
fix d3 selection in xmux4 CI #57: Commit 87055fe pushed by gadfort
February 15, 2024 20:06 40s fix-muxes
fix-muxes
February 15, 2024 20:06 40s
add org lambdalib file as comment CI #56: Commit b9bf381 pushed by gadfort
February 15, 2024 17:54 34s main
main
February 15, 2024 17:54 34s
fix yosys run to avoid names surelog doesnt like CI #55: Commit fed3dda pushed by gadfort
February 15, 2024 16:55 39s main
main
February 15, 2024 16:55 39s
Merge pull request #38 from siliconcompiler/generate CI #54: Commit 38fb24e pushed by gadfort
February 15, 2024 16:18 38s main
main
February 15, 2024 16:18 38s
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