Merge pull request #71 from siliconcompiler/iocut

add ring cut notion to padring
siliconcompiler · Aug 27, 2024 · 47854f0 · 47854f0
2 parents 46300ec + f432a54
commit 47854f0
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Showing 2 changed files with 58 additions and 7 deletions.
diff --git a/lambdalib/iolib/rtl/la_iocut.v b/lambdalib/iolib/rtl/la_iocut.v
@@ -16,9 +16,16 @@ module la_iocut
     )
    (
     // ground never cut
-    inout vss
+    inout             vss,   // core ground
+    // cut these
+    inout             vdd0,   // core supply from section before
+    inout             vdd1,   // core supply from next section
+    inout             vddio0, // io supply from section before
+    inout             vddio1, // io supply from next section
+    inout             vssio0, // io ground from section before
+    inout             vssio1, // io ground from next section
+    inout [RINGW-1:0] ioring0,// generic ioring interface from section before
+    inout [RINGW-1:0] ioring1 // generic ioring interface from next section
     );
 
-   // TODO: interface?
-
 endmodule
diff --git a/lambdalib/padring/rtl/la_ioside.v b/lambdalib/padring/rtl/la_ioside.v
@@ -207,10 +207,54 @@ module la_ioside
         // LA_CUT
         if (CELLMAP[(i*40+16)+:8] == LA_CUT)
           begin : icut
-             la_iocut #(.SIDE (SIDE),
-                        .PROP (CELLMAP[(i*40+32)+:8]),
-                        .RINGW(RINGW))
-             i0 (.vss(vss));
+             if (i - 1 < 0 && i + 1 == NCELLS)
+              begin: icut_invalid
+              end
+             if (i - 1 < 0 && i + 1 <= NCELLS - 1)
+              begin: icut_start
+                la_iocut #(.SIDE(SIDE),
+                           .PROP(CELLMAP[(i*40+32)+:8]),
+                           .RINGW(RINGW))
+                i0 (.vss(vss),
+                    .vdd0(),
+                    .vdd1(vdd[CELLMAP[((i + 1)*40+24)+:8]]),
+                    .vddio0(),
+                    .vddio1(vddio[CELLMAP[((i + 1)*40+24)+:8]]),
+                    .vssio0(),
+                    .vssio1(vssio[CELLMAP[((i + 1)*40+24)+:8]]),
+                    .ioring0(),
+                    .ioring1(ioring[CELLMAP[((i + 1)*40+24)+:8]*RINGW+:RINGW]));
+              end
+             if (i - 1 >= 0 && i + 1 <= NCELLS - 1)
+              begin: icut_middle
+                la_iocut #(.SIDE(SIDE),
+                           .PROP(CELLMAP[(i*40+32)+:8]),
+                           .RINGW(RINGW))
+                i0 (.vss(vss),
+                    .vdd0(vdd[CELLMAP[((i - 1)*40+24)+:8]]),
+                    .vdd1(vdd[CELLMAP[((i + 1)*40+24)+:8]]),
+                    .vddio0(vddio[CELLMAP[((i - 1)*40+24)+:8]]),
+                    .vddio1(vddio[CELLMAP[((i + 1)*40+24)+:8]]),
+                    .vssio0(vssio[CELLMAP[((i - 1)*40+24)+:8]]),
+                    .vssio1(vssio[CELLMAP[((i + 1)*40+24)+:8]]),
+                    .ioring0(ioring[CELLMAP[((i - 1)*40+24)+:8]*RINGW+:RINGW]),
+                    .ioring1(ioring[CELLMAP[((i + 1)*40+24)+:8]*RINGW+:RINGW]));
+              end
+             if (i - 1 >= 0 && i + 1 == NCELLS)
+              begin: icut_end
+                la_iocut #(.SIDE(SIDE),
+                           .PROP(CELLMAP[(i*40+32)+:8]),
+                           .RINGW(RINGW))
+                i0 (.vss(vss),
+                    .vdd0(vdd[CELLMAP[((i - 1)*40+24)+:8]]),
+                    .vdd1(),
+                    .vddio0(vddio[CELLMAP[((i - 1)*40+24)+:8]]),
+                    .vddio1(),
+                    .vssio0(vssio[CELLMAP[((i - 1)*40+24)+:8]]),
+                    .vssio1(),
+                    .ioring0(ioring[CELLMAP[((i - 1)*40+24)+:8]*RINGW+:RINGW]),
+                    .ioring1());
+              end
           end
         // LA_VDDIO
         if (CELLMAP[(i*40+16)+:8] == LA_VDDIO)