diff --git a/lambdalib/ramlib/ramlib.py b/lambdalib/ramlib/ramlib.py
index 21e18bd..3cb701d 100644
--- a/lambdalib/ramlib/ramlib.py
+++ b/lambdalib/ramlib/ramlib.py
@@ -2,14 +2,14 @@
 import siliconcompiler
 from siliconcompiler.flows import lintflow
 
+
 def setup(chip, path=None):
 
-    # setup verilog
-    files = glob.glob(f'rtl/*.v')
+    files = glob.glob('rtl/*.v')
     for item in files:
         chip.input(item)
 
-###########################
+
 if __name__ == "__main__":
 
     design = "la_syncfifo"
diff --git a/lambdalib/stdlib/stdlib.py b/lambdalib/stdlib/stdlib.py
index 1fd6e5d..9a1691f 100644
--- a/lambdalib/stdlib/stdlib.py
+++ b/lambdalib/stdlib/stdlib.py
@@ -2,14 +2,14 @@
 import siliconcompiler
 from siliconcompiler.flows import lintflow
 
+
 def setup(chip, path=None):
 
-    # setup verilog
-    files = glob.glob(f'rtl/*.v')
+    files = glob.glob('rtl/*.v')
     for item in files:
         chip.input(item)
 
-###########################
+
 if __name__ == "__main__":
 
     design = "la_inv"