packetize lambdapdk

.flake8

@@ -0,0 +1,4 @@
+[flake8]
+max-line-length = 100
+extend-exclude = build, dist, lambdapdk/gf180/base/klayout
+

.github/workflows/ci.yml

@@ -0,0 +1,33 @@
+name: Lint
+on:
+  # Runs on all pushes to branches
+  push:
+  # Runs on all PRs
+  pull_request:
+  # Manual Dispatch
+  workflow_dispatch:
+
+jobs:
+  lint_python:
+    name: Lint Python Code
+    runs-on: ubuntu-latest
+    steps:
+      - name: Check out Git repository
+        uses: actions/checkout@v4
+      - name: Lint with Flake8
+        run: |
+          pip install --upgrade pip
+          pip install .[dev]
+          flake8 --statistics .
+
+  check_paths:
+    name: Run CI
+    runs-on: ubuntu-latest
+    steps:
+      - name: Check out Git repository
+        uses: actions/checkout@v4
+      - name: Run tests
+        run: |
+          pip install --upgrade pip
+          pip install -e .[dev]
+          pytest

.github/workflows/wheels.yml

@@ -0,0 +1,39 @@
+name: Wheels
+
+on:
+  workflow_dispatch:
+  release:
+    types:
+      - published
+
+jobs:
+  build_wheels:
+    name: Wheels lambdalib
+    runs-on: ubuntu-latest
+
+    steps:
+    - uses: actions/checkout@v4
+      with:
+        submodules: true
+    - uses: hynek/build-and-inspect-python-package@v1
+
+  publish:
+    needs: [build_wheels]
+    runs-on: ubuntu-latest
+    if: github.event_name == 'release' && github.event.action == 'published' && !contains(github.event.release.body, 'NOPUBLISH')
+
+    steps:
+    - uses: actions/download-artifact@v3
+      with:
+        name: artifact
+        path: dist
+
+    - uses: pypa/gh-action-pypi-publish@v1.4.2
+      with:
+        user: __token__
+        password: ${{ secrets.PYPI_DEPLOY }}
+
+    - name: Add wheels to GitHub release artifacts
+      uses: softprops/action-gh-release@v1
+      with:
+        files: dist/*.whl

.gitignore

@@ -9,6 +9,9 @@ a.out
 
 # Byte-compiled / optimized / DLL files
 __pycache__/
+*.egg-info/
+dist/
 
 # sc files
 build/
+lambdapdk/_version.py

MANIFEST.in

@@ -0,0 +1,7 @@
+# stuff we need to include into the sdist is handled automatically by
+# setuptools_scm - it includes all git-committed files.
+# but we want to exclude some committed files/dirs not needed in the sdist:
+prune .github
+prune scripts
+prune lambdapdk/*/base
+prune lambdapdk/*/libs/*

lambdapdk/__init__.py

@@ -0,0 +1,18 @@
+import os
+__version__ = "0.1.0"
+
+
+def register_data_source(chip):
+    # check if local
+    root_path = os.path.dirname(os.path.dirname(__file__))
+    test_path = os.path.join(root_path, 'lambdapdk', 'asap7', 'base', 'apr', 'asap7_tech.lef')
+    if os.path.exists(test_path):
+        path = root_path
+        ref = None
+    else:
+        path = 'git+https://github.com/silicompiler/lambdapdk.git'
+        ref = f'v{__version__}'
+
+    chip.register_package_source(name='lambdapdk',
+                                 path=path,
+                                 ref=ref)

lambdapdk/asap7/__init__.py

@@ -0,0 +1,115 @@
+import os
+import siliconcompiler
+from lambdapdk import register_data_source
+
+
+####################################################
+# PDK Setup
+####################################################
+def setup(chip):
+    '''
+    The asap7 PDK was developed at ASU in collaboration with ARM Research.
+    With funding from the DARPA IDEA program, the PDK was released
+    a permissive open source PDK in 2021. The PDK contains SPICE-compatible
+    FinFET device models (BSIM-CMG), Technology files for Cadence Virtuoso,
+    Design Rule Checker (DRC), Layout vs Schematic Checker (LVS) and
+    Extraction Deck for the 7nm technology node. For more details regarding
+    the technical specifications of the PDK, please refer the PDK
+    documentation and associated publication. Note that this process
+    design kit is provided as an academic and research aid only and the
+    resulting designs are not manufacturable.
+
+    PDK content:
+
+    * open source DRM
+    * device primitive library (virtuoso)
+    * spice (hspice)
+    * extraction runsets (calibre)
+    * drc runsets (calibre)
+    * APR technology files
+    * 7.5 track multi-vt standard cell libraries
+
+    More information:
+
+    * https://asap.asu.edu/
+    * L.T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline,
+      C. Ramamurthya, and G. Yeric, “ASAP7: A 7-nm FinFET Predictive Process
+      Design Kit,” Microelectronics Journal, vol. 53, pp. 105-115, July 2016.
+
+
+    Sources: https://github.com/The-OpenROAD-Project/asap7
+
+    .. warning::
+       Work in progress (not ready for use)
+    '''
+
+    foundry = 'virtual'
+    process = 'asap7'
+    node = 7
+    rev = 'r1p7'
+    stackup = '10M'
+    wafersize = 300
+    libtype = '7p5t'
+    pdkdir = os.path.join('lambdapdk', 'asap7', 'base')
+
+    register_data_source(chip)
+    pdk = siliconcompiler.PDK(chip, process, package='lambdapdk')
+
+    # process name
+    pdk.set('pdk', process, 'foundry', foundry)
+    pdk.set('pdk', process, 'node', node)
+    pdk.set('pdk', process, 'wafersize', wafersize)
+    pdk.set('pdk', process, 'version', rev)
+    pdk.set('pdk', process, 'stackup', stackup)
+
+    # APR tech file
+    for tool in ('openroad', 'klayout', 'magic'):
+        pdk.set('pdk', process, 'aprtech', tool, stackup, libtype, 'lef',
+                pdkdir + '/apr/asap7_tech.lef')
+
+    pdk.set('pdk', process, 'minlayer', stackup, 'M2')
+    pdk.set('pdk', process, 'maxlayer', stackup, 'M7')
+
+    # Klayout setup file
+    pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'klayout', stackup,
+            pdkdir + '/setup/klayout/asap7.lyt')
+
+    pdk.set('pdk', process, 'display', 'klayout', stackup,
+            pdkdir + '/setup/klayout/asap7.lyp')
+
+    # Openroad global routing grid derating
+    openroad_layer_adjustments = {
+        'M1': 1.0,
+        'M2': 0.8,
+        'M3': 0.7,
+        'M4': 0.4,
+        'M5': 0.4,
+        'M6': 0.4,
+        'M7': 0.4,
+        'M8': 0.4,
+        'M9': 0.4,
+        'Pad': 1.0
+    }
+    for layer, adj in openroad_layer_adjustments.items():
+        pdk.set('pdk', process, 'var', 'openroad', f'{layer}_adjustment', stackup, str(adj))
+
+    pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'M3')
+    pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'M3')
+
+    pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'M5')
+    pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'M4')
+
+    # PEX
+    pdk.set('pdk', process, 'pexmodel', 'openroad', stackup, 'typical',
+            pdkdir + '/pex/openroad/typical.tcl')
+    pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, 'typical',
+            pdkdir + '/pex/openroad/typical.rules')
+
+    return pdk
+
+
+#########################
+if __name__ == "__main__":
+    pdk = setup(siliconcompiler.Chip('<pdk>'))
+    register_data_source(pdk)
+    pdk.check_filepaths()

lambdapdk/asap7/libs/asap7sc7p5t.py

@@ -0,0 +1,139 @@
+import os
+import siliconcompiler
+from lambdapdk import register_data_source
+
+
+def _setup_lib(chip, libname, suffix):
+    register_data_source(chip)
+    lib = siliconcompiler.Library(chip, libname, package='lambdapdk')
+
+    process = 'asap7'
+    stackup = '10M'
+    libtype = '7p5t'
+    rev = 'r1p7'
+    corners = {'typical': 'tt',
+               'fast': 'ff',
+               'slow': 'ss'}
+
+    libdir = os.path.join('lambdapdk', process, 'libs', libname)
+
+    # rev
+    lib.set('package', 'version', rev)
+
+    # todo: remove later
+    lib.set('option', 'pdk', process)
+
+    # timing
+    for corner_name, lib_corner in corners.items():
+        lib.add('output', corner_name, 'nldm',
+                libdir + '/nldm/' + libname + '_' + lib_corner + '.lib.gz')
+
+    # lef
+    lib.add('output', stackup, 'lef', libdir + '/lef/' + libname + '.lef')
+
+    # gds
+    lib.add('output', stackup, 'gds', libdir + '/gds/' + libname + '.gds')
+
+    # cdl
+    lib.add('output', stackup, 'cdl', libdir + '/netlist/' + libname + '.cdl')
+
+    # lib arch
+    lib.set('asic', 'libarch', libtype)
+
+    # site name
+    lib.set('asic', 'site', libtype, 'asap7sc7p5t')
+
+    # clock buffers
+    lib.add('asic', 'cells', 'clkbuf', f"BUFx2_ASAP7_75t_{suffix}")
+
+    # tie cells
+    lib.add('asic', 'cells', 'tie', [f"TIEHIx1_ASAP7_75t_{suffix}",
+                                     f"TIELOx1_ASAP7_75t_{suffix}"])
+
+    # hold cells
+    lib.add('asic', 'cells', 'hold', f"BUFx2_ASAP7_75t_{suffix}")
+
+    # filler
+    lib.add('asic', 'cells', 'filler', [f"FILLER_ASAP7_75t_{suffix}",
+                                        f"FILLERxp5_ASAP7_75t_{suffix}"])
+
+    # decap
+    lib.add('asic', 'cells', 'decap', [f"DECAPx1_ASAP7_75t_{suffix}",
+                                       f"DECAPx1_ASAP7_75t_{suffix}",
+                                       f"DECAPx3_ASAP7_75t_{suffix}",
+                                       f"DECAPx6_ASAP7_75t_{suffix}",
+                                       f"DECAPx10_ASAP7_75t_{suffix}"])
+
+    # Stupid small cells
+    lib.add('asic', 'cells', 'dontuse', ["[!ASYNC]*x1_ASAP7*",
+                                         "*x1p*_ASAP7*",
+                                         "*xp*_ASAP7*",
+                                         "SDF*",
+                                         "ICG*",
+                                         "DFFH*"])
+
+    # Tapcell
+    lib.add('asic', 'cells', 'tap', f"TAPCELL_ASAP7_75t_{suffix}")
+
+    # Endcap
+    lib.add('asic', 'cells', 'endcap', f"DECAPx1_ASAP7_75t_{suffix}")
+
+    # Yosys techmap
+    lib.add('option', 'file', 'yosys_techmap', libdir + '/techmap/yosys/cells_latch.v')
+    lib.add('option', 'file', 'yosys_addermap', libdir + '/techmap/yosys/cells_adders.v')
+    lib.set('option', 'file', 'yosys_dff_liberty',
+            libdir + '/nldm/' + libname + '_' + 'ss.lib.gz')
+
+    # Defaults for OpenROAD tool variables
+    lib.set('option', 'var', 'openroad_place_density', '0.60')
+    lib.set('option', 'var', 'openroad_pad_global_place', '2')
+    lib.set('option', 'var', 'openroad_pad_detail_place', '1')
+    lib.set('option', 'var', 'openroad_macro_place_halo', ['10', '10'])
+    lib.set('option', 'var', 'openroad_macro_place_channel', ['12', '12'])
+
+    lib.set('option', 'var', 'openroad_cts_clock_buffer', f"BUFx4_ASAP7_75t_{suffix}")
+    lib.set('option', 'var', 'openroad_cts_distance_between_buffers', "60")
+
+    lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1")  # convert from ps -> ps
+    lib.set('option', 'var', 'yosys_driver_cell', f"BUFx2_ASAP7_75t_{suffix}")
+    lib.set('option', 'var', 'yosys_buffer_cell', f"BUFx2_ASAP7_75t_{suffix}")
+    lib.set('option', 'var', 'yosys_buffer_input', "A")
+    lib.set('option', 'var', 'yosys_buffer_output', "Y")
+    for tool in ('yosys', 'openroad'):
+        lib.set('option', 'var', f'{tool}_tiehigh_cell', f"TIEHIx1_ASAP7_75t_{suffix}")
+        lib.set('option', 'var', f'{tool}_tiehigh_port', "H")
+        lib.set('option', 'var', f'{tool}_tielow_cell', f"TIELOx1_ASAP7_75t_{suffix}")
+        lib.set('option', 'var', f'{tool}_tielow_port', "L")
+
+    # Openroad APR setup files
+    lib.set('option', 'file', 'openroad_tracks', libdir + '/apr/openroad/tracks.tcl')
+    lib.set('option', 'file', 'openroad_tapcells', libdir + '/apr/openroad/tapcells.tcl')
+    lib.set('option', 'file', 'openroad_pdngen', libdir + '/apr/openroad/pdngen.tcl')
+    lib.set('option', 'file', 'openroad_global_connect',
+            libdir + '/apr/openroad/global_connect.tcl')
+
+    return lib
+
+
+def setup(chip):
+    '''
+    ASAP 7 7.5-track standard cell library.
+    '''
+    all_libs = {
+        'asap7sc7p5t_rvt': 'R',
+        'asap7sc7p5t_lvt': 'L',
+        'asap7sc7p5t_slvt': 'SL'
+    }
+
+    libs = []
+    for libname, suffix in all_libs.items():
+        libs.append(_setup_lib(chip, libname, suffix))
+
+    return libs
+
+
+#########################
+if __name__ == "__main__":
+    for lib in setup(siliconcompiler.Chip('<lib>')):
+        register_data_source(lib)
+        lib.check_filepaths()