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add ihp130 enablement
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@gadfort
gadfort committed Sep 19, 2024
1 parent a9dc4dc commit cfc9bb7
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8 changes: 5 additions & 3 deletions lambdapdk/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -20,10 +20,10 @@ def get_pdks():
Returns a list of pdk names in lambdapdk
'''

from lambdapdk import asap7, freepdk45, sky130, gf180
from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130

all_pdks = []
for pdk_mod in [asap7, freepdk45, sky130, gf180]:
for pdk_mod in [asap7, freepdk45, sky130, gf180, ihp130]:
pdks = pdk_mod.setup()
if not isinstance(pdks, (list, tuple)):
pdks = [pdks]
Expand All @@ -42,13 +42,15 @@ def get_libs():
from lambdapdk.freepdk45.libs import nangate45, fakeram45
from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram
from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram
from lambdapdk.ihp130.libs import sg13g2_stdcell, sg13g2_sram

all_libs = []
for lib_mod in [
asap7sc7p5t, fakeram7, fakeio7,
nangate45, fakeram45,
sky130sc, sky130io, sky130sram,
gf180mcu, gf180io, gf180sram]:
gf180mcu, gf180io, gf180sram,
sg13g2_stdcell, sg13g2_sram]:
libs = lib_mod.setup()
if not isinstance(libs, (list, tuple)):
libs = [libs]
Expand Down
133 changes: 133 additions & 0 deletions lambdapdk/ihp130/__init__.py
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@@ -0,0 +1,133 @@

import os
import siliconcompiler
from lambdapdk import register_data_source


pdk_rev = '89c8038db331ccfdf6be488dfc4670cb62ba3c42'


def register_ihp130_data_source(chip):
chip.register_source(
'ihp130',
path='git+https://github.com/IHP-GmbH/IHP-Open-PDK',
ref=pdk_rev)


####################################################
# PDK Setup
####################################################
def setup():
'''
130nm BiCMOS Open Source PDK, dedicated for Analog/Digital, Mixed Signal and RF Design
IHP Open Source PDK project goal is to provide a fully open source Process Design Kit and
related data, which can be used to create manufacturable designs at IHP's facility.
SG13G2 is a high performance BiCMOS technology with a 0.13 μm CMOS process.
It contains bipolar devices based on SiGe:C npn-HBT's with up to 350 GHz transition frequency
(fT) and 450 GHz oscillation frequency (fmax).
This process provides 2 gate oxides:
A thin gate oxide for the 1.2 V digital logic and a thick oxide for a 3.3 V supply voltage.
For both modules NMOS, PMOS and isolated NMOS transistors are offered.
Further passive components like poly silicon resistors and MIM capacitors are available.
The backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm thick) and
a MIM layer.
Sources:
* https://github.com/IHP-GmbH/IHP-Open-PDK
'''

foundry = 'Leibniz-Institut für innovative Mikroelektronik'
process = 'ihp130'
stackup = '5M2TL'

node = 130
# TODO: dummy numbers, only matter for cost estimation
wafersize = 300
hscribe = 0.1
vscribe = 0.1
edgemargin = 2

lpdkdir = os.path.join('lambdapdk', 'ihp130', 'base')

pdk = siliconcompiler.PDK(process, package='ihp130')
register_ihp130_data_source(pdk)
register_data_source(pdk)

# process name
pdk.set('pdk', process, 'foundry', foundry)
pdk.set('pdk', process, 'node', node)
pdk.set('pdk', process, 'version', pdk_rev)
pdk.set('pdk', process, 'stackup', stackup)
pdk.set('pdk', process, 'wafersize', wafersize)
pdk.set('pdk', process, 'edgemargin', edgemargin)
pdk.set('pdk', process, 'scribe', (hscribe, vscribe))

# APR Setup
# TODO: remove libtype
for tool in ('openroad', 'klayout', 'magic'):
# Add unithd for backwards compatibility
pdk.set('pdk', process, 'aprtech', tool, stackup, '9t', 'lef',
'ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef')

pdk.set('pdk', process, 'minlayer', stackup, 'Metal2')
pdk.set('pdk', process, 'maxlayer', stackup, 'Metal5')

# DRC Runsets
# pdk.set('pdk', process, 'drc', 'runset', 'magic', stackup, 'basic',
# pdkdir + '/setup/magic/sky130A.tech')

# LVS Runsets
# pdk.set('pdk', process, 'lvs', 'runset', 'netgen', stackup, 'basic',
# pdkdir + '/setup/netgen/lvs_setup.tcl')

# Layer map and display file
pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'klayout', stackup,
'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt')
pdk.set('pdk', process, 'display', 'klayout', stackup,
'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp')

pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'gds', stackup,
'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.map')

# Openroad global routing grid derating
openroad_layer_adjustments = {
'Metal1': 0.05,
'Metal2': 0.05,
'Metal3': 0.05,
'Metal4': 0.05,
'Metal5': 0.05,
'TopMetal1': 0.00,
'TopMetal2': 0.00,
}
for layer, adj in openroad_layer_adjustments.items():
pdk.set('pdk', process, 'var', 'openroad', f'{layer}_adjustment', stackup, str(adj))

pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'Metal2')
pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'Metal5')

pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'Metal3')
pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'Metal2')

# PEX
for corner in ["typical"]:
pdk.set('pdk', process, 'pexmodel', 'openroad', stackup, corner,
lpdkdir + '/pex/openroad/' + corner + '.tcl', package='lambdapdk')
pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, corner,
lpdkdir + '/pex/openroad/' + corner + '.rules', package='lambdapdk')

# Documentation
pdk.set('pdk', process, 'doc', 'overview',
'ihp-sg13g2/libs.doc/doc/SG13G2_os_process_spec.pdf')
pdk.set('pdk', process, 'doc', 'drc_rules',
'ihp-sg13g2/libs.doc/doc/SG13G2_os_layout_rules.pdf')

return pdk


#########################
if __name__ == "__main__":
pdk = setup(siliconcompiler.Chip('<pdk>'))
pdk.write_manifest(f'{pdk.top()}.json')
105 changes: 105 additions & 0 deletions lambdapdk/ihp130/base/dfm/fill.json
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{
"layers" : {
"Metal1" : {
"layer": 8,
"datatype": 0,
"name": "Metal1",
"space_to_outline": 0,
"non-opc": {
"datatype": 22,
"width": [2.0],
"height": [5.0],
"space_to_fill": 1.2,
"space_to_non_fill": 1.0
}
},

"Metal2" : {
"layer": 10,
"datatype": 0,
"name": "Metal2",
"space_to_outline": 0,
"non-opc": {
"datatype": 22,
"width": [5.0],
"height": [2.0],
"space_to_fill": 1.2,
"space_to_non_fill": 1.0
}
},

"Metal3" : {
"layer": 30,
"datatype": 0,
"name": "Metal3",
"space_to_outline": 0,
"non-opc": {
"datatype": 22,
"width": [2.0],
"height": [5.0],
"space_to_fill": 1.2,
"space_to_non_fill": 1.0
}
},

"Metal4" : {
"layer": 50,
"datatype": 0,
"name": "Metal4",
"space_to_outline": 0,
"non-opc": {
"datatype": 22,
"width": [5.0],
"height": [2.0],
"space_to_fill": 1.2,
"space_to_non_fill": 1.0
}
},

"Metal5" : {
"layer": 67,
"datatype": 0,
"name": "Metal5",
"space_to_outline": 0,
"non-opc": {
"datatype": 22,
"width": [2.0],
"height": [5.0],
"space_to_fill": 1.2,
"space_to_non_fill": 1.0
}
},

"TopMetal1" : {
"layer": 126,
"datatype": 0,
"name": "TopMetal1",
"space_to_outline": 0,
"non-opc": {
"datatype": 22,
"width": [10.0],
"height": [ 5.0],
"space_to_fill": 3.0,
"space_to_non_fill": 4.9
}
},

"TopMetal2" : {
"layer": 134,
"datatype": 0,
"name": "TopMetal2",
"space_to_outline": 0,
"non-opc": {
"datatype": 22,
"width": [ 5.0],
"height": [10.0],
"space_to_fill": 3.0,
"space_to_non_fill": 4.9
}
}
},
"outline" : {
"layer": 39,
"datatype": 4
}
}
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