diff --git a/lambdapdk/__init__.py b/lambdapdk/__init__.py index 551622c0..238bd2a5 100644 --- a/lambdapdk/__init__.py +++ b/lambdapdk/__init__.py @@ -20,10 +20,10 @@ def get_pdks(): Returns a list of pdk names in lambdapdk ''' - from lambdapdk import asap7, freepdk45, sky130, gf180 + from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130 all_pdks = [] - for pdk_mod in [asap7, freepdk45, sky130, gf180]: + for pdk_mod in [asap7, freepdk45, sky130, gf180, ihp130]: pdks = pdk_mod.setup() if not isinstance(pdks, (list, tuple)): pdks = [pdks] @@ -42,13 +42,15 @@ def get_libs(): from lambdapdk.freepdk45.libs import nangate45, fakeram45 from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram + from lambdapdk.ihp130.libs import sg13g2_stdcell, sg13g2_sram all_libs = [] for lib_mod in [ asap7sc7p5t, fakeram7, fakeio7, nangate45, fakeram45, sky130sc, sky130io, sky130sram, - gf180mcu, gf180io, gf180sram]: + gf180mcu, gf180io, gf180sram, + sg13g2_stdcell, sg13g2_sram]: libs = lib_mod.setup() if not isinstance(libs, (list, tuple)): libs = [libs] diff --git a/lambdapdk/ihp130/__init__.py b/lambdapdk/ihp130/__init__.py new file mode 100644 index 00000000..0a244290 --- /dev/null +++ b/lambdapdk/ihp130/__init__.py @@ -0,0 +1,133 @@ + +import os +import siliconcompiler +from lambdapdk import register_data_source + + +pdk_rev = '89c8038db331ccfdf6be488dfc4670cb62ba3c42' + + +def register_ihp130_data_source(chip): + chip.register_source( + 'ihp130', + path='git+https://github.com/IHP-GmbH/IHP-Open-PDK', + ref=pdk_rev) + + +#################################################### +# PDK Setup +#################################################### +def setup(): + ''' + 130nm BiCMOS Open Source PDK, dedicated for Analog/Digital, Mixed Signal and RF Design + + IHP Open Source PDK project goal is to provide a fully open source Process Design Kit and + related data, which can be used to create manufacturable designs at IHP's facility. + + SG13G2 is a high performance BiCMOS technology with a 0.13 μm CMOS process. + It contains bipolar devices based on SiGe:C npn-HBT's with up to 350 GHz transition frequency + (fT) and 450 GHz oscillation frequency (fmax). + This process provides 2 gate oxides: + A thin gate oxide for the 1.2 V digital logic and a thick oxide for a 3.3 V supply voltage. + For both modules NMOS, PMOS and isolated NMOS transistors are offered. + Further passive components like poly silicon resistors and MIM capacitors are available. + The backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm thick) and + a MIM layer. + + Sources: + + * https://github.com/IHP-GmbH/IHP-Open-PDK + ''' + + foundry = 'Leibniz-Institut für innovative Mikroelektronik' + process = 'ihp130' + stackup = '5M2TL' + + node = 130 + # TODO: dummy numbers, only matter for cost estimation + wafersize = 300 + hscribe = 0.1 + vscribe = 0.1 + edgemargin = 2 + + lpdkdir = os.path.join('lambdapdk', 'ihp130', 'base') + + pdk = siliconcompiler.PDK(process, package='ihp130') + register_ihp130_data_source(pdk) + register_data_source(pdk) + + # process name + pdk.set('pdk', process, 'foundry', foundry) + pdk.set('pdk', process, 'node', node) + pdk.set('pdk', process, 'version', pdk_rev) + pdk.set('pdk', process, 'stackup', stackup) + pdk.set('pdk', process, 'wafersize', wafersize) + pdk.set('pdk', process, 'edgemargin', edgemargin) + pdk.set('pdk', process, 'scribe', (hscribe, vscribe)) + + # APR Setup + # TODO: remove libtype + for tool in ('openroad', 'klayout', 'magic'): + # Add unithd for backwards compatibility + pdk.set('pdk', process, 'aprtech', tool, stackup, '9t', 'lef', + 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef') + + pdk.set('pdk', process, 'minlayer', stackup, 'Metal2') + pdk.set('pdk', process, 'maxlayer', stackup, 'Metal5') + + # DRC Runsets +# pdk.set('pdk', process, 'drc', 'runset', 'magic', stackup, 'basic', +# pdkdir + '/setup/magic/sky130A.tech') + + # LVS Runsets +# pdk.set('pdk', process, 'lvs', 'runset', 'netgen', stackup, 'basic', +# pdkdir + '/setup/netgen/lvs_setup.tcl') + + # Layer map and display file + pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'klayout', stackup, + 'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt') + pdk.set('pdk', process, 'display', 'klayout', stackup, + 'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp') + + pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'gds', stackup, + 'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.map') + + # Openroad global routing grid derating + openroad_layer_adjustments = { + 'Metal1': 0.05, + 'Metal2': 0.05, + 'Metal3': 0.05, + 'Metal4': 0.05, + 'Metal5': 0.05, + 'TopMetal1': 0.00, + 'TopMetal2': 0.00, + } + for layer, adj in openroad_layer_adjustments.items(): + pdk.set('pdk', process, 'var', 'openroad', f'{layer}_adjustment', stackup, str(adj)) + + pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'Metal2') + pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'Metal5') + + pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'Metal3') + pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'Metal2') + + # PEX + for corner in ["typical"]: + pdk.set('pdk', process, 'pexmodel', 'openroad', stackup, corner, + lpdkdir + '/pex/openroad/' + corner + '.tcl', package='lambdapdk') + pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, corner, + lpdkdir + '/pex/openroad/' + corner + '.rules', package='lambdapdk') + + # Documentation + pdk.set('pdk', process, 'doc', 'overview', + 'ihp-sg13g2/libs.doc/doc/SG13G2_os_process_spec.pdf') + pdk.set('pdk', process, 'doc', 'drc_rules', + 'ihp-sg13g2/libs.doc/doc/SG13G2_os_layout_rules.pdf') + + return pdk + + +######################### +if __name__ == "__main__": + pdk = setup(siliconcompiler.Chip('')) + pdk.write_manifest(f'{pdk.top()}.json') diff --git a/lambdapdk/ihp130/base/dfm/fill.json b/lambdapdk/ihp130/base/dfm/fill.json new file mode 100644 index 00000000..fb8c7079 --- /dev/null +++ b/lambdapdk/ihp130/base/dfm/fill.json @@ -0,0 +1,105 @@ +{ + "layers" : { + "Metal1" : { + "layer": 8, + "datatype": 0, + "name": "Metal1", + "space_to_outline": 0, + "non-opc": { + "datatype": 22, + "width": [2.0], + "height": [5.0], + "space_to_fill": 1.2, + "space_to_non_fill": 1.0 + } + }, + + "Metal2" : { + "layer": 10, + "datatype": 0, + "name": "Metal2", + "space_to_outline": 0, + "non-opc": { + "datatype": 22, + "width": [5.0], + "height": [2.0], + "space_to_fill": 1.2, + "space_to_non_fill": 1.0 + } + }, + + "Metal3" : { + "layer": 30, + "datatype": 0, + "name": "Metal3", + "space_to_outline": 0, + "non-opc": { + "datatype": 22, + "width": [2.0], + "height": [5.0], + "space_to_fill": 1.2, + "space_to_non_fill": 1.0 + } + }, + + "Metal4" : { + "layer": 50, + "datatype": 0, + "name": "Metal4", + "space_to_outline": 0, + "non-opc": { + "datatype": 22, + "width": [5.0], + "height": [2.0], + "space_to_fill": 1.2, + "space_to_non_fill": 1.0 + } + }, + + "Metal5" : { + "layer": 67, + "datatype": 0, + "name": "Metal5", + "space_to_outline": 0, + "non-opc": { + "datatype": 22, + "width": [2.0], + "height": [5.0], + "space_to_fill": 1.2, + "space_to_non_fill": 1.0 + } + }, + + "TopMetal1" : { + "layer": 126, + "datatype": 0, + "name": "TopMetal1", + "space_to_outline": 0, + "non-opc": { + "datatype": 22, + "width": [10.0], + "height": [ 5.0], + "space_to_fill": 3.0, + "space_to_non_fill": 4.9 + } + }, + + "TopMetal2" : { + "layer": 134, + "datatype": 0, + "name": "TopMetal2", + "space_to_outline": 0, + "non-opc": { + "datatype": 22, + "width": [ 5.0], + "height": [10.0], + "space_to_fill": 3.0, + "space_to_non_fill": 4.9 + } + } + }, + "outline" : { + "layer": 39, + "datatype": 4 + } +} \ No newline at end of file diff --git a/lambdapdk/ihp130/base/pex/openroad/typical.rules b/lambdapdk/ihp130/base/pex/openroad/typical.rules new file mode 100644 index 00000000..f5b733d8 --- /dev/null +++ b/lambdapdk/ihp130/base/pex/openroad/typical.rules @@ -0,0 +1,2267 @@ +Extraction Rules for OpenRCX + +DIAGMODEL ON + +LayerCount 7 +DensityRate 1 0 + +DensityModel 0 + +Metal 1 RESOVER +WIDTH Table 1 entries: 0.16 + +Metal 1 RESOVER 0 +DIST count 55 width 0.16 +0 0 0 0.0006875 +0 0.26 0 0.0006875 +0 0.42 0 0.0006875 +0 0.6 0 0.0006875 +0 0.68 0 0.0006875 +0 0.84 0 0.0006875 +0 1.02 0 0.0006875 +0 1.1 0 0.0006875 +0 1.26 0 0.0006875 +0 1.68 0 0.0006875 +0.26 0.26 0 0.0006875 +0.26 0.42 0 0.0006875 +0.26 0.6 0 0.0006875 +0.26 0.68 0 0.0006875 +0.26 0.84 0 0.0006875 +0.26 1.02 0 0.0006875 +0.26 1.1 0 0.0006875 +0.26 1.26 0 0.0006875 +0.26 1.68 0 0.0006875 +0.42 0.42 0 0.0006875 +0.42 0.6 0 0.0006875 +0.42 0.68 0 0.0006875 +0.42 0.84 0 0.0006875 +0.42 1.02 0 0.0006875 +0.42 1.1 0 0.0006875 +0.42 1.26 0 0.0006875 +0.42 1.68 0 0.0006875 +0.6 0.6 0 0.0006875 +0.6 0.68 0 0.0006875 +0.6 0.84 0 0.0006875 +0.6 1.02 0 0.0006875 +0.6 1.1 0 0.0006875 +0.6 1.26 0 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6.57717e-05 0.00022 +0.945 0 6.36533e-05 0.00022 +1.05 0 6.20462e-05 0.00022 +1.26 0 5.95409e-05 0.00022 +1.68 0 5.71694e-05 0.00022 +2.1 0 5.74624e-05 0.00022 +2.52 0 5.93899e-05 0.00022 +END DIST + +Metal 2 OVER 1 UNDER 7 +DIST count 12 width 0.2 +0.21 0.000116769 1.84348e-05 0.00022 +0.42 0 8.76803e-05 0.00022 +0.525 0 7.69551e-05 0.00022 +0.63 0 7.18409e-05 0.00022 +0.735 0 6.80553e-05 0.00022 +0.84 0 6.53591e-05 0.00022 +0.945 0 6.33321e-05 0.00022 +1.05 0 6.18391e-05 0.00022 +1.26 0 5.95242e-05 0.00022 +1.68 0 5.7099e-05 0.00022 +2.1 0 5.69639e-05 0.00022 +2.52 0 5.83538e-05 0.00022 +END DIST + +Metal 3 RESOVER +WIDTH Table 1 entries: 0.2 + +Metal 3 RESOVER 0 +DIST count 55 width 0.2 +0 0 0 0.00044 +0 0.22 0 0.00044 +0 0.42 0 0.00044 +0 0.54 0 0.00044 +0 0.64 0 0.00044 +0 0.84 0 0.00044 +0 0.96 0 0.00044 +0 1.06 0 0.00044 +0 1.26 0 0.00044 +0 1.68 0 0.00044 +0.22 0.22 0 0.00044 +0.22 0.42 0 0.00044 +0.22 0.54 0 0.00044 +0.22 0.64 0 0.00044 +0.22 0.84 0 0.00044 +0.22 0.96 0 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6.19975e-05 0.00022 +0.945 0 5.94235e-05 0.00022 +1.05 0 5.69205e-05 0.00022 +1.26 0 5.42823e-05 0.00022 +1.68 0 5.15018e-05 0.00022 +2.1 0 4.99874e-05 0.00022 +2.52 0 4.86699e-05 0.00022 +END DIST + +Metal 3 UNDER +WIDTH Table 1 entries: 0.2 + +Metal 3 UNDER 4 +DIST count 12 width 0.2 +0.21 0.000116661 1.78864e-05 0.00022 +0.42 0 8.74283e-05 0.00022 +0.525 0 7.62455e-05 0.00022 +0.63 0 7.2997e-05 0.00022 +0.735 0 6.84616e-05 0.00022 +0.84 0 6.54947e-05 0.00022 +0.945 0 6.33162e-05 0.00022 +1.05 0 6.14285e-05 0.00022 +1.26 0 5.48412e-05 0.00022 +1.68 0 5.38306e-05 0.00022 +2.1 0 5.50202e-05 0.00022 +2.52 0 5.6799e-05 0.00022 +END DIST + +Metal 3 UNDER 5 +DIST count 12 width 0.2 +0.21 0.000119315 1.54747e-05 0.00022 +0.42 0 8.48593e-05 0.00022 +0.525 0 7.44884e-05 0.00022 +0.63 0 6.79684e-05 0.00022 +0.735 0 6.24811e-05 0.00022 +0.84 0 5.86768e-05 0.00022 +0.945 0 5.5724e-05 0.00022 +1.05 0 5.35414e-05 0.00022 +1.26 0 5.02053e-05 0.00022 +1.68 0 4.63965e-05 0.00022 +2.1 0 4.42003e-05 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width 0.2 +0.21 0.000118911 1.74846e-05 0.00022 +0.42 0 8.70788e-05 0.00022 +0.525 0 7.74379e-05 0.00022 +0.63 0 7.15995e-05 0.00022 +0.735 0 6.69672e-05 0.00022 +0.84 0 6.36389e-05 0.00022 +0.945 0 6.10505e-05 0.00022 +1.05 0 5.87854e-05 0.00022 +1.26 0 5.59717e-05 0.00022 +1.68 0 5.29563e-05 0.00022 +2.1 0 5.1396e-05 0.00022 +2.52 0 5.02096e-05 0.00022 +END DIST + +Metal 4 RESOVER +WIDTH Table 1 entries: 0.2 + +Metal 4 RESOVER 0 +DIST count 55 width 0.2 +0 0 0 0.00044 +0 0.22 0 0.00044 +0 0.42 0 0.00044 +0 0.54 0 0.00044 +0 0.64 0 0.00044 +0 0.84 0 0.00044 +0 0.96 0 0.00044 +0 1.06 0 0.00044 +0 1.26 0 0.00044 +0 1.68 0 0.00044 +0.22 0.22 0 0.00044 +0.22 0.42 0 0.00044 +0.22 0.54 0 0.00044 +0.22 0.64 0 0.00044 +0.22 0.84 0 0.00044 +0.22 0.96 0 0.00044 +0.22 1.06 0 0.00044 +0.22 1.26 0 0.00044 +0.22 1.68 0 0.00044 +0.42 0.42 0 0.00044 +0.42 0.54 0 0.00044 +0.42 0.64 0 0.00044 +0.42 0.84 0 0.00044 +0.42 0.96 0 0.00044 +0.42 1.06 0 0.00044 +0.42 1.26 0 0.00044 +0.42 1.68 0 0.00044 +0.54 0.54 0 0.00044 +0.54 0.64 0 0.00044 +0.54 0.84 0 0.00044 +0.54 0.96 0 0.00044 +0.54 1.06 0 0.00044 +0.54 1.26 0 0.00044 +0.54 1.68 0 0.00044 +0.64 0.64 0 0.00044 +0.64 0.84 0 0.00044 +0.64 0.96 0 0.00044 +0.64 1.06 0 0.00044 +0.64 1.26 0 0.00044 +0.64 1.68 0 0.00044 +0.84 0.84 0 0.00044 +0.84 0.96 0 0.00044 +0.84 1.06 0 0.00044 +0.84 1.26 0 0.00044 +0.84 1.68 0 0.00044 +0.96 0.96 0 0.00044 +0.96 1.06 0 0.00044 +0.96 1.26 0 0.00044 +0.96 1.68 0 0.00044 +1.06 1.06 0 0.00044 +1.06 1.26 0 0.00044 +1.06 1.68 0 0.00044 +1.26 1.26 0 0.00044 +1.26 1.68 0 0.00044 +1.68 0 1.68 0.00044 +END DIST + +Metal 4 RESOVER 1 +DIST count 0 width 0.2 +END DIST + +Metal 4 RESOVER 2 +DIST count 0 width 0.2 +END DIST + +Metal 4 RESOVER 3 +DIST count 0 width 0.2 +END DIST + +Metal 4 OVER +WIDTH Table 1 entries: 0.2 + +Metal 4 OVER 0 +DIST count 12 width 0.2 +0.21 0.000117063 1.6504e-05 0.00022 +0.42 0 8.37598e-05 0.00022 +0.525 0 7.34409e-05 0.00022 +0.63 0 6.66609e-05 0.00022 +0.735 0 6.07748e-05 0.00022 +0.84 0 5.67237e-05 0.00022 +0.945 0 5.34864e-05 0.00022 +1.05 0 5.08869e-05 0.00022 +1.26 0 4.70702e-05 0.00022 +1.68 0 4.25177e-05 0.00022 +2.1 0 3.97424e-05 0.00022 +2.52 0 3.77386e-05 0.00022 +END DIST + +Metal 4 OVER 1 +DIST count 12 width 0.2 +0.21 0.000123821 1.08154e-05 0.00022 +0.42 0 8.38472e-05 0.00022 +0.525 0 7.3701e-05 0.00022 +0.63 0 6.70644e-05 0.00022 +0.735 0 6.16624e-05 0.00022 +0.84 0 5.76833e-05 0.00022 +0.945 0 5.44593e-05 0.00022 +1.05 0 5.18303e-05 0.00022 +1.26 0 4.78992e-05 0.00022 +1.68 0 4.31866e-05 0.00022 +2.1 0 4.04467e-05 0.00022 +2.52 0 3.85861e-05 0.00022 +END DIST + +Metal 4 OVER 2 +DIST count 12 width 0.2 +0.21 0.000119645 1.53384e-05 0.00022 +0.42 0 8.4323e-05 0.00022 +0.525 0 7.42957e-05 0.00022 +0.63 0 6.77437e-05 0.00022 +0.735 0 6.24452e-05 0.00022 +0.84 0 5.85664e-05 0.00022 +0.945 0 5.54538e-05 0.00022 +1.05 0 5.41528e-05 0.00022 +1.26 0 5.02177e-05 0.00022 +1.68 0 4.5521e-05 0.00022 +2.1 0 4.2874e-05 0.00022 +2.52 0 4.1123e-05 0.00022 +END DIST + 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0.00022 +0.735 0 6.30626e-05 0.00022 +0.84 0 5.91424e-05 0.00022 +0.945 0 5.60232e-05 0.00022 +1.05 0 5.42563e-05 0.00022 +1.26 0 5.03667e-05 0.00022 +1.68 0 4.56088e-05 0.00022 +2.1 0 4.29811e-05 0.00022 +2.52 0 4.13747e-05 0.00022 +END DIST + +Metal 4 UNDER 7 +DIST count 12 width 0.2 +0.21 0.00011867 1.5452e-05 0.00022 +0.42 0 8.35263e-05 0.00022 +0.525 0 7.3474e-05 0.00022 +0.63 0 6.68422e-05 0.00022 +0.735 0 6.14225e-05 0.00022 +0.84 0 5.73944e-05 0.00022 +0.945 0 5.41268e-05 0.00022 +1.05 0 5.09179e-05 0.00022 +1.26 0 4.71104e-05 0.00022 +1.68 0 4.26333e-05 0.00022 +2.1 0 3.99705e-05 0.00022 +2.52 0 3.80785e-05 0.00022 +END DIST + +Metal 4 DIAGUNDER +WIDTH Table 1 entries: 0.2 + +Metal 4 DIAGUNDER 5 +DIST count 13 width 0.2 +0 0 0 0.00022 +0.21 0 0 0.00022 +0.42 0 0 0.00022 +0.525 0 0 0.00022 +0.63 0 0 0.00022 +0.735 0 0 0.00022 +0.84 0 0 0.00022 +0.945 0 0 0.00022 +1.05 0 0 0.00022 +1.26 0 0 0.00022 +1.68 0 0 0.00022 +2.1 0 0 0.00022 +2.52 0 0 0.00022 +END DIST + +Metal 4 DIAGUNDER 6 +DIST count 13 width 0.2 +0 0 0 0.00022 +0.21 0 0 0.00022 +0.42 0 0 0.00022 +0.525 0 0 0.00022 +0.63 0 0 0.00022 +0.735 0 0 0.00022 +0.84 0 0 0.00022 +0.945 0 0 0.00022 +1.05 0 0 0.00022 +1.26 0 0 0.00022 +1.68 0 0 0.00022 +2.1 0 0 0.00022 +2.52 0 0 0.00022 +END DIST + +Metal 4 DIAGUNDER 7 +DIST count 13 width 0.2 +0 0 0 0.00022 +0.21 0 0 0.00022 +0.42 0 0 0.00022 +0.525 0 0 0.00022 +0.63 0 0 0.00022 +0.735 0 0 0.00022 +0.84 0 0 0.00022 +0.945 0 0 0.00022 +1.05 0 0 0.00022 +1.26 0 0 0.00022 +1.68 0 0 0.00022 +2.1 0 0 0.00022 +2.52 0 0 0.00022 +END DIST + +Metal 4 OVERUNDER +WIDTH Table 1 entries: 0.2 + +Metal 4 OVER 1 UNDER 5 +DIST count 12 width 0.2 +0.21 0.000120521 1.47121e-05 0.00022 +0.42 0 8.74818e-05 0.00022 +0.525 0 7.6599e-05 0.00022 +0.63 0 7.17422e-05 0.00022 +0.735 0 6.82033e-05 0.00022 +0.84 0 6.57078e-05 0.00022 +0.945 0 6.37947e-05 0.00022 +1.05 0 6.28444e-05 0.00022 +1.26 0 5.99975e-05 0.00022 +1.68 0 5.6948e-05 0.00022 +2.1 0 5.58972e-05 0.00022 +2.52 0 5.59856e-05 0.00022 +END DIST + +Metal 4 OVER 1 UNDER 6 +DIST count 12 width 0.2 +0.21 0.000126321 9.6697e-06 0.00022 +0.42 0 8.50831e-05 0.00022 +0.525 0 7.50616e-05 0.00022 +0.63 0 6.85593e-05 0.00022 +0.735 0 6.35275e-05 0.00022 +0.84 0 5.97134e-05 0.00022 +0.945 0 5.66366e-05 0.00022 +1.05 0 5.45472e-05 0.00022 +1.26 0 5.06717e-05 0.00022 +1.68 0 4.59487e-05 0.00022 +2.1 0 4.337e-05 0.00022 +2.52 0 4.18737e-05 0.00022 +END DIST + +Metal 4 OVER 1 UNDER 7 +DIST count 12 width 0.2 +0.21 0.000122596 1.18268e-05 0.00022 +0.42 0 8.3478e-05 0.00022 +0.525 0 7.34775e-05 0.00022 +0.63 0 6.69672e-05 0.00022 +0.735 0 6.18462e-05 0.00022 +0.84 0 5.79056e-05 0.00022 +0.945 0 5.46763e-05 0.00022 +1.05 0 5.17232e-05 0.00022 +1.26 0 4.77997e-05 0.00022 +1.68 0 4.31636e-05 0.00022 +2.1 0 4.05384e-05 0.00022 +2.52 0 3.87735e-05 0.00022 +END DIST + +Metal 4 OVER 2 UNDER 5 +DIST count 12 width 0.2 +0.21 0.000117089 2.0929e-05 0.00022 +0.42 0 9.11033e-05 0.00022 +0.525 0 8.01263e-05 0.00022 +0.63 0 7.52268e-05 0.00022 +0.735 0 7.14912e-05 0.00022 +0.84 0 6.9023e-05 0.00022 +0.945 0 6.71641e-05 0.00022 +1.05 0 6.73146e-05 0.00022 +1.26 0 6.42177e-05 0.00022 +1.68 0 6.05674e-05 0.00022 +2.1 0 5.90073e-05 0.00022 +2.52 0 5.86912e-05 0.00022 +END DIST + +Metal 4 OVER 2 UNDER 6 +DIST count 12 width 0.2 +0.21 0.000123027 1.18265e-05 0.00022 +0.42 0 8.39871e-05 0.00022 +0.525 0 7.39755e-05 0.00022 +0.63 0 6.75333e-05 0.00022 +0.735 0 6.26182e-05 0.00022 +0.84 0 5.89376e-05 0.00022 +0.945 0 5.59982e-05 0.00022 +1.05 0 5.50409e-05 0.00022 +1.26 0 5.11583e-05 0.00022 +1.68 0 4.64293e-05 0.00022 +2.1 0 4.39061e-05 0.00022 +2.52 0 4.24301e-05 0.00022 +END DIST + +Metal 4 OVER 2 UNDER 7 +DIST count 12 width 0.2 +0.21 0.000121046 1.40606e-05 0.00022 +0.42 0 8.42972e-05 0.00022 +0.525 0 7.43869e-05 0.00022 +0.63 0 6.78558e-05 0.00022 +0.735 0 6.27167e-05 0.00022 +0.84 0 5.8799e-05 0.00022 +0.945 0 5.56366e-05 0.00022 +1.05 0 5.33503e-05 0.00022 +1.26 0 4.95482e-05 0.00022 +1.68 0 4.51768e-05 0.00022 +2.1 0 4.28003e-05 0.00022 +2.52 0 4.1247e-05 0.00022 +END DIST + +Metal 4 OVER 3 UNDER 5 +DIST count 12 width 0.2 +0.21 0.000113864 2.68465e-05 0.00022 +0.42 0 9.59182e-05 0.00022 +0.525 0 8.66361e-05 0.00022 +0.63 0 8.50732e-05 0.00022 +0.735 0 8.23121e-05 0.00022 +0.84 0 8.078e-05 0.00022 +0.945 0 7.98088e-05 0.00022 +1.05 0 8.28515e-05 0.00022 +1.26 0 8.05141e-05 0.00022 +1.68 0 7.80404e-05 0.00022 +2.1 0 7.66222e-05 0.00022 +2.52 0 7.58371e-05 0.00022 +END DIST + +Metal 4 OVER 3 UNDER 6 +DIST count 12 width 0.2 +0.21 0.000121555 1.41861e-05 0.00022 +0.42 0 8.67699e-05 0.00022 +0.525 0 7.7553e-05 0.00022 +0.63 0 7.19015e-05 0.00022 +0.735 0 6.76051e-05 0.00022 +0.84 0 6.44533e-05 0.00022 +0.945 0 6.05237e-05 0.00022 +1.05 0 5.94149e-05 0.00022 +1.26 0 5.56598e-05 0.00022 +1.68 0 5.16593e-05 0.00022 +2.1 0 4.98432e-05 0.00022 +2.52 0 4.90126e-05 0.00022 +END DIST + +Metal 4 OVER 3 UNDER 7 +DIST count 12 width 0.2 +0.21 0.000118494 1.69732e-05 0.00022 +0.42 0 8.63331e-05 0.00022 +0.525 0 7.70119e-05 0.00022 +0.63 0 7.11513e-05 0.00022 +0.735 0 6.66227e-05 0.00022 +0.84 0 6.32932e-05 0.00022 +0.945 0 5.94129e-05 0.00022 +1.05 0 5.69803e-05 0.00022 +1.26 0 5.35455e-05 0.00022 +1.68 0 5.012e-05 0.00022 +2.1 0 4.84508e-05 0.00022 +2.52 0 4.75182e-05 0.00022 +END DIST + +Metal 5 RESOVER +WIDTH Table 1 entries: 0.2 + +Metal 5 RESOVER 0 +DIST count 55 width 0.2 +0 0 0 0.00044 +0 0.22 0 0.00044 +0 0.42 0 0.00044 +0 0.54 0 0.00044 +0 0.64 0 0.00044 +0 0.84 0 0.00044 +0 0.96 0 0.00044 +0 1.06 0 0.00044 +0 1.26 0 0.00044 +0 1.68 0 0.00044 +0.22 0.22 0 0.00044 +0.22 0.42 0 0.00044 +0.22 0.54 0 0.00044 +0.22 0.64 0 0.00044 +0.22 0.84 0 0.00044 +0.22 0.96 0 0.00044 +0.22 1.06 0 0.00044 +0.22 1.26 0 0.00044 +0.22 1.68 0 0.00044 +0.42 0.42 0 0.00044 +0.42 0.54 0 0.00044 +0.42 0.64 0 0.00044 +0.42 0.84 0 0.00044 +0.42 0.96 0 0.00044 +0.42 1.06 0 0.00044 +0.42 1.26 0 0.00044 +0.42 1.68 0 0.00044 +0.54 0.54 0 0.00044 +0.54 0.64 0 0.00044 +0.54 0.84 0 0.00044 +0.54 0.96 0 0.00044 +0.54 1.06 0 0.00044 +0.54 1.26 0 0.00044 +0.54 1.68 0 0.00044 +0.64 0.64 0 0.00044 +0.64 0.84 0 0.00044 +0.64 0.96 0 0.00044 +0.64 1.06 0 0.00044 +0.64 1.26 0 0.00044 +0.64 1.68 0 0.00044 +0.84 0.84 0 0.00044 +0.84 0.96 0 0.00044 +0.84 1.06 0 0.00044 +0.84 1.26 0 0.00044 +0.84 1.68 0 0.00044 +0.96 0.96 0 0.00044 +0.96 1.06 0 0.00044 +0.96 1.26 0 0.00044 +0.96 1.68 0 0.00044 +1.06 1.06 0 0.00044 +1.06 1.26 0 0.00044 +1.06 1.68 0 0.00044 +1.26 1.26 0 0.00044 +1.26 1.68 0 0.00044 +1.68 0 1.68 0.00044 +END DIST + +Metal 5 RESOVER 1 +DIST count 0 width 0.2 +END DIST + +Metal 5 RESOVER 2 +DIST count 0 width 0.2 +END DIST + +Metal 5 RESOVER 3 +DIST count 0 width 0.2 +END DIST + +Metal 5 RESOVER 4 +DIST count 0 width 0.2 +END DIST + +Metal 5 OVER +WIDTH Table 1 entries: 0.2 + +Metal 5 OVER 0 +DIST count 12 width 0.2 +0.21 0.000117766 1.60253e-05 0.00022 +0.42 0 8.39548e-05 0.00022 +0.525 0 7.34139e-05 0.00022 +0.63 0 6.67114e-05 0.00022 +0.735 0 6.04063e-05 0.00022 +0.84 0 5.68455e-05 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DIST + +Metal 6 OVER 2 UNDER 7 +DIST count 12 width 1.64 +1.64 6.83511e-05 3.06514e-05 5.4878e-06 +3.28 2.85904e-05 4.71869e-05 5.4878e-06 +4.1 2.34777e-05 4.50278e-05 5.4878e-06 +4.92 1.85764e-05 4.78271e-05 5.4878e-06 +5.74 8.53443e-06 6.1053e-05 5.4878e-06 +6.56 1.09694e-05 5.26654e-05 5.4878e-06 +7.38 4.95008e-06 5.86682e-05 5.4878e-06 +8.2 0 6.34142e-05 5.4878e-06 +9.84 0 6.4664e-05 5.4878e-06 +13.12 0 6.48087e-05 5.4878e-06 +16.4 0 6.48087e-05 5.4878e-06 +19.68 0 6.48087e-05 5.4878e-06 +END DIST + +Metal 6 OVER 3 UNDER 7 +DIST count 12 width 1.64 +1.64 6.73222e-05 3.26333e-05 5.4878e-06 +3.28 2.70988e-05 5.03392e-05 5.4878e-06 +4.1 2.17996e-05 4.83636e-05 5.4878e-06 +4.92 1.67911e-05 5.1342e-05 5.4878e-06 +5.74 6.93927e-06 6.45572e-05 5.4878e-06 +6.56 9.69786e-06 5.60717e-05 5.4878e-06 +7.38 2.12765e-06 6.3848e-05 5.4878e-06 +8.2 0 6.59597e-05 5.4878e-06 +9.84 0 6.73531e-05 5.4878e-06 +13.12 0 6.7588e-05 5.4878e-06 +16.4 0 6.7588e-05 5.4878e-06 +19.68 0 6.75881e-05 5.4878e-06 +END DIST + +Metal 6 OVER 4 UNDER 7 +DIST count 12 width 1.64 +1.64 6.55744e-05 4.12319e-05 5.4878e-06 +3.28 2.53605e-05 5.97906e-05 5.4878e-06 +4.1 2.055e-05 5.77773e-05 5.4878e-06 +4.92 1.5812e-05 6.0956e-05 5.4878e-06 +5.74 6.20917e-06 7.42989e-05 5.4878e-06 +6.56 9.01506e-06 6.60247e-05 5.4878e-06 +7.38 0 7.54034e-05 5.4878e-06 +8.2 0 7.54704e-05 5.4878e-06 +9.84 0 7.68537e-05 5.4878e-06 +13.12 0 7.70526e-05 5.4878e-06 +16.4 0 7.70526e-05 5.4878e-06 +19.68 0 7.70526e-05 5.4878e-06 +END DIST + +Metal 6 OVER 5 UNDER 7 +DIST count 12 width 1.64 +1.64 5.93777e-05 6.38545e-05 5.4878e-06 +3.28 1.9814e-05 8.57286e-05 5.4878e-06 +4.1 1.09842e-05 9.28007e-05 5.4878e-06 +4.92 8.26762e-06 9.90626e-05 5.4878e-06 +5.74 0 0.000106505 5.4878e-06 +6.56 0 0.00010578 5.4878e-06 +7.38 0 0.000105009 5.4878e-06 +8.2 0 0.000104734 5.4878e-06 +9.84 0 0.000104841 5.4878e-06 +13.12 0 0.000103091 5.4878e-06 +16.4 0 0.000103091 5.4878e-06 +19.68 0 0.000103091 5.4878e-06 +END DIST + +Metal 7 RESOVER +WIDTH Table 1 entries: 2 + +Metal 7 RESOVER 0 +DIST count 55 width 2 +0 0 0 5.50001e-06 +0 2 0 5.50001e-06 +0 4 0 5.50001e-06 +0 5 0 5.50001e-06 +0 6 0 5.50001e-06 +0 8 0 5.50001e-06 +0 9 0 5.50001e-06 +0 10 0 5.50001e-06 +0 12 0 5.50001e-06 +0 16 0 5.50001e-06 +2 2 0 5.50001e-06 +2 4 0 5.50001e-06 +2 5 0 5.50001e-06 +2 6 0 5.50001e-06 +2 8 0 5.50001e-06 +2 9 0 5.50001e-06 +2 10 0 5.50001e-06 +2 12 0 5.50001e-06 +2 16 0 5.50001e-06 +4 4 0 5.50001e-06 +4 5 0 5.50001e-06 +4 6 0 5.50001e-06 +4 8 0 5.50001e-06 +4 9 0 5.50001e-06 +4 10 0 5.50001e-06 +4 12 0 5.50001e-06 +4 16 0 5.50001e-06 +5 5 0 5.50001e-06 +5 6 0 5.50001e-06 +5 8 0 5.50001e-06 +5 9 0 5.50001e-06 +5 10 0 5.50001e-06 +5 12 0 5.50001e-06 +5 16 0 5.50001e-06 +6 6 0 5.50001e-06 +6 8 0 5.50001e-06 +6 9 0 5.50001e-06 +6 10 0 5.50001e-06 +6 12 0 5.50001e-06 +6 16 0 5.50001e-06 +8 8 0 5.50001e-06 +8 9 0 5.50001e-06 +8 10 0 5.50001e-06 +8 12 0 5.50001e-06 +8 16 0 5.50001e-06 +9 9 0 5.50001e-06 +9 10 0 5.50001e-06 +9 12 0 5.50001e-06 +9 16 0 5.50001e-06 +10 10 0 5.50001e-06 +10 12 0 5.50001e-06 +10 16 0 5.50001e-06 +12 12 0 5.50001e-06 +12 16 0 5.50001e-06 +16 0 16 5.50001e-06 +END DIST + +Metal 7 RESOVER 1 +DIST count 0 width 2 +END DIST + +Metal 7 RESOVER 2 +DIST count 0 width 2 +END DIST + +Metal 7 RESOVER 3 +DIST count 0 width 2 +END DIST + +Metal 7 RESOVER 4 +DIST count 0 width 2 +END DIST + +Metal 7 RESOVER 5 +DIST count 0 width 2 +END DIST + +Metal 7 RESOVER 6 +DIST count 0 width 2 +END DIST + +Metal 7 OVER +WIDTH Table 1 entries: 2 + +Metal 7 OVER 0 +DIST count 12 width 2 +2 8.1604e-05 7.24629e-06 2.75e-06 +4 4.41274e-05 9.92581e-06 2.75e-06 +5 3.81093e-05 9.94455e-06 2.75e-06 +6 3.25353e-05 1.0766e-05 2.75e-06 +7 2.69718e-05 1.32245e-05 2.75e-06 +8 2.52373e-05 1.29741e-05 2.75e-06 +9 2.39568e-05 1.26904e-05 2.75e-06 +10 2.29594e-05 1.24337e-05 2.75e-06 +12 0 3.07541e-05 2.75e-06 +16 0 3.07541e-05 2.75e-06 +20 0 3.07541e-05 2.75e-06 +24 0 3.07541e-05 2.75e-06 +END DIST + +Metal 7 OVER 1 +DIST count 12 width 2 +2 7.45985e-05 1.43366e-05 2.75e-06 +4 3.88404e-05 1.53318e-05 2.75e-06 +5 3.29227e-05 1.50702e-05 2.75e-06 +6 2.74371e-05 1.60626e-05 2.75e-06 +7 2.47073e-05 1.58154e-05 2.75e-06 +8 2.2164e-05 1.63875e-05 2.75e-06 +9 2.02831e-05 1.68046e-05 2.75e-06 +10 1.88927e-05 1.71074e-05 2.75e-06 +12 0 3.15281e-05 2.75e-06 +16 0 3.15281e-05 2.75e-06 +20 0 3.15281e-05 2.75e-06 +24 0 3.15281e-05 2.75e-06 +END DIST + +Metal 7 OVER 2 +DIST count 12 width 2 +2 7.44625e-05 1.44819e-05 2.75e-06 +4 3.85471e-05 1.5735e-05 2.75e-06 +5 3.25693e-05 1.57041e-05 2.75e-06 +6 2.71511e-05 1.6646e-05 2.75e-06 +7 2.4555e-05 1.61638e-05 2.75e-06 +8 2.21859e-05 1.64584e-05 2.75e-06 +9 2.05406e-05 1.65943e-05 2.75e-06 +10 1.948e-05 1.6583e-05 2.75e-06 +12 0 3.22289e-05 2.75e-06 +16 0 3.22289e-05 2.75e-06 +20 0 3.22289e-05 2.75e-06 +24 0 3.22289e-05 2.75e-06 +END DIST + +Metal 7 OVER 3 +DIST count 12 width 2 +2 7.44181e-05 1.47576e-05 2.75e-06 +4 3.83149e-05 1.62192e-05 2.75e-06 +5 3.25327e-05 1.61492e-05 2.75e-06 +6 2.70899e-05 1.71902e-05 2.75e-06 +7 2.4369e-05 1.68146e-05 2.75e-06 +8 2.18542e-05 1.71995e-05 2.75e-06 +9 2.00463e-05 1.74388e-05 2.75e-06 +10 1.87331e-05 1.76226e-05 2.75e-06 +12 0 3.30136e-05 2.75e-06 +16 0 3.30136e-05 2.75e-06 +20 0 3.30136e-05 2.75e-06 +24 0 3.30136e-05 2.75e-06 +END DIST + +Metal 7 OVER 4 +DIST count 12 width 2 +2 7.40968e-05 1.52738e-05 2.75e-06 +4 3.758e-05 1.73759e-05 2.75e-06 +5 3.16282e-05 1.75117e-05 2.75e-06 +6 2.61642e-05 1.86382e-05 2.75e-06 +7 2.33633e-05 1.84488e-05 2.75e-06 +8 2.07459e-05 1.90725e-05 2.75e-06 +9 1.87466e-05 1.96971e-05 2.75e-06 +10 1.71705e-05 2.04409e-05 2.75e-06 +12 0 3.40878e-05 2.75e-06 +16 0 3.40878e-05 2.75e-06 +20 0 3.40878e-05 2.75e-06 +24 0 3.40878e-05 2.75e-06 +END DIST + +Metal 7 OVER 5 +DIST count 12 width 2 +2 7.47594e-05 1.48189e-05 2.75e-06 +4 3.71166e-05 1.83327e-05 2.75e-06 +5 3.0871e-05 1.8857e-05 2.75e-06 +6 2.5439e-05 2.00727e-05 2.75e-06 +7 2.28398e-05 1.97999e-05 2.75e-06 +8 2.05404e-05 2.01559e-05 2.75e-06 +9 1.88889e-05 2.03421e-05 2.75e-06 +10 1.76711e-05 2.04487e-05 2.75e-06 +12 0 3.53802e-05 2.75e-06 +16 0 3.53802e-05 2.75e-06 +20 0 3.53802e-05 2.75e-06 +24 0 3.53802e-05 2.75e-06 +END DIST + +Metal 7 OVER 6 +DIST count 12 width 2 +2 6.13143e-05 3.4642e-05 2.75e-06 +4 2.87743e-05 3.63013e-05 2.75e-06 +5 2.3231e-05 3.73049e-05 2.75e-06 +6 1.85049e-05 3.87129e-05 2.75e-06 +7 1.66686e-05 3.74496e-05 2.75e-06 +8 1.48182e-05 3.78617e-05 2.75e-06 +9 1.36624e-05 3.79932e-05 2.75e-06 +10 1.29836e-05 3.79624e-05 2.75e-06 +12 0 5.00848e-05 2.75e-06 +16 0 5.00848e-05 2.75e-06 +20 0 5.00848e-05 2.75e-06 +24 0 5.00848e-05 2.75e-06 +END DIST + +Metal 7 UNDER +WIDTH Table 0 entries: + +Metal 7 DIAGUNDER +WIDTH Table 0 entries: +END DensityModel 0 \ No newline at end of file diff --git a/lambdapdk/ihp130/base/pex/openroad/typical.tcl b/lambdapdk/ihp130/base/pex/openroad/typical.tcl new file mode 100644 index 00000000..ab3be6b1 --- /dev/null +++ b/lambdapdk/ihp130/base/pex/openroad/typical.tcl @@ -0,0 +1,17 @@ +# correlateRC.py gcd,ibex,aes,jpeg,chameleon,riscv32i,chameleon_hier +# cap units pf/um +set_layer_rc {{ corner }} -layer Metal1 -capacitance 3.49E-05 -resistance 0.135e-03 +set_layer_rc {{ corner }} -layer Metal2 -capacitance 1.81E-05 -resistance 0.103e-03 +set_layer_rc {{ corner }} -layer Metal3 -capacitance 2.14962E-04 -resistance 0.103e-03 +set_layer_rc {{ corner }} -layer Metal4 -capacitance 1.48128E-04 -resistance 0.103e-03 +set_layer_rc {{ corner }} -layer Metal5 -capacitance 1.54087E-04 -resistance 0.103e-03 +set_layer_rc {{ corner }} -layer TopMetal1 -capacitance 1.54087E-04 -resistance 0.021e-03 +set_layer_rc {{ corner }} -layer TopMetal2 -capacitance 1.54087E-04 -resistance 0.0145e-03 +# end correlate + +set_layer_rc {{ corner }} -via Via1 -resistance 2.0E-3 +set_layer_rc {{ corner }} -via Via2 -resistance 2.0E-3 +set_layer_rc {{ corner }} -via Via3 -resistance 2.0E-3 +set_layer_rc {{ corner }} -via Via4 -resistance 2.0E-3 +set_layer_rc {{ corner }} -via TopVia1 -resistance 0.4E-3 +set_layer_rc {{ corner }} -via TopVia2 -resistance 0.22E-3 diff --git a/lambdapdk/ihp130/libs/sg13g2_sram.py b/lambdapdk/ihp130/libs/sg13g2_sram.py new file mode 100644 index 00000000..ee1174ba --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_sram.py @@ -0,0 +1,46 @@ +from siliconcompiler import Chip, Library +from lambdapdk import register_data_source +from lambdapdk.ihp130 import register_ihp130_data_source + + +def setup(): + libs = [] + stackup = '5M2TL' + + for config in ('1024x64', '2048x64', '256x48', '256x64', '512x64', '64x64'): + mem_name = f'RM_IHPSG13_1P_{config}_c2_bm_bist' + lib = Library(mem_name, package='ihp130') + register_ihp130_data_source(lib) + register_data_source(lib) + path_base = 'ihp-sg13g2/libs.ref/sg13g2_sram' + lib.add('output', stackup, 'lef', f'{path_base}/lef/{mem_name}.lef') + lib.add('output', stackup, 'gds', f'{path_base}/gds/{mem_name}.gds') + lib.add('output', stackup, 'cdl', f'{path_base}/spice/{mem_name}.cdl') + + lib.add('output', 'typ', 'nldm', f'{path_base}/lib/{mem_name}_typ_1p20V_25C.lib') + lib.add('output', 'slow', 'nldm', f'{path_base}/lib/{mem_name}_slow_1p08V_125C.lib') + lib.add('output', 'fast', 'nldm', f'{path_base}/lib/{mem_name}_fast_1p32V_m55C.lib') + + lib.add('output', 'rtl', 'verilog', f'{path_base}/verilog/{mem_name}.v') + lib.add('output', 'rtl', 'verilog', + f'{path_base}/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v') + + lib.set('option', 'file', 'openroad_pdngen', + 'lambdapdk/ihp130/libs/sg13g2_sram/pdngen.tcl', + package='lambdapdk') + + libs.append(lib) + + lambda_lib = Library('lambdalib_sg13g2_sram', package='lambdapdk') + register_data_source(lambda_lib) + lambda_lib.add('option', 'ydir', 'lambdapdk/ihp130/libs/sg13g2_sram/lambda') + + libs.append(lambda_lib) + + return libs + + +######################### +if __name__ == "__main__": + for lib in setup(Chip('')): + lib.write_manifest(f'{lib.top()}.json') diff --git a/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_asyncfifo.v b/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_asyncfifo.v new file mode 100644 index 00000000..3d37a974 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_asyncfifo.v @@ -0,0 +1,195 @@ +/***************************************************************************** + * Function: Dual Clock Asynchronous FIFO + * Copyright: Lambda Project Authors. All rights Reserved. + * License: MIT (see LICENSE file in Lambda repository) + * + * Docs: + * + * This is a wrapper for selecting from a set of hardened memory macros. + * + * A synthesizable reference model is used when the TYPE is DEFAULT. The + * synthesizable model does not implement the cfg and test interface and should + * only be used for basic testing and for synthesizing for FPGA devices. + * Advanced ASIC development should rely on complete functional models + * supplied on a per macro basis. + * + * Technologoy specific implementations of "la_dpram" would generally include + * one ore more hardcoded instantiations of RAM modules with a generate + * statement relying on the "TYPE" to select between the list of modules + * at build time. + * + ****************************************************************************/ + +module la_asyncfifo #( + parameter DW = 32, // Memory width + parameter DEPTH = 4, // FIFO depth + parameter NS = 1, // Number of power supplies + parameter CTRLW = 1, // width of asic ctrl interface + parameter TESTW = 1, // width of asic teset interface + parameter CHAOS = 0, // generates random full logic when set + parameter TYPE = "DEFAULT" // Pass through variable for hard macro +) ( // write port + input wr_clk, + input wr_nreset, + input [ DW-1:0] wr_din, // data to write + input wr_en, // write fifo + input wr_chaosmode, // randomly assert fifo full when set + output reg wr_full, // fifo full + // read port + input rd_clk, + input rd_nreset, + output [ DW-1:0] rd_dout, // output data (next cycle) + input rd_en, // read fifo + output reg rd_empty, // fifo is empty + // Power signals + input vss, // ground signal + input [ NS-1:0] vdd, // supplies + // Generic interfaces + input [CTRLW-1:0] ctrl, // pass through ASIC control interface + input [TESTW-1:0] test // pass through ASIC test interface +); + + // local params + // The last part is to support DEPTH of 1 + localparam AW = $clog2(DEPTH) + {31'h0, (DEPTH == 1)}; + + // local wires + reg [AW:0] wr_grayptr; + reg [AW:0] wr_binptr; + reg [AW:0] wr_binptr_mem; + wire [AW:0] wr_grayptr_nxt; + wire [AW:0] wr_binptr_nxt; + wire [AW:0] wr_binptr_mem_nxt; + wire [AW:0] wr_grayptr_sync; + wire wr_chaosfull; + + reg [AW:0] rd_grayptr; + reg [AW:0] rd_binptr; + reg [AW:0] rd_binptr_mem; + wire [AW:0] rd_grayptr_nxt; + wire [AW:0] rd_binptr_nxt; + wire [AW:0] rd_binptr_mem_nxt; + wire [AW:0] rd_grayptr_sync; + + genvar i; + + //########################### + //# WRITE SIDE LOGIC + //########################### + + always @(posedge wr_clk or negedge wr_nreset) + if (~wr_nreset) begin + wr_binptr_mem[AW:0] <= 'b0; + wr_binptr[AW:0] <= 'b0; + wr_grayptr[AW:0] <= 'b0; + end else begin + wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0]; + wr_binptr[AW:0] <= wr_binptr_nxt[AW:0]; + wr_grayptr[AW:0] <= wr_grayptr_nxt[AW:0]; + end + + // Update binary pointer on write and not full + assign wr_binptr_mem_nxt[AW:0] = wr_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (wr_en && ~wr_full)}; + assign wr_binptr_nxt[AW:0] = wr_binptr[AW:0] + {{AW{1'b0}}, (wr_en && ~wr_full)}; + + // Convert binary point to gray pointer for sync + assign wr_grayptr_nxt[AW:0] = wr_binptr_nxt[AW:0] ^ {1'b0, wr_binptr_nxt[AW:1]}; + + // Full comparison (gray pointer based) + // Amir - add support for fifo DEPTH that is not power of 2 + // Note - the previous logic also had a bug that full was high one entry to soon + + reg [AW:0] rd_binptr_sync; + wire [AW:0] fifo_used; + integer j; + + always @(*) begin + rd_binptr_sync[AW] = rd_grayptr_sync[AW]; + for (j = AW; j > 0; j = j - 1) + rd_binptr_sync[j-1] = rd_binptr_sync[j] ^ rd_grayptr_sync[j-1]; + end + + assign fifo_used = wr_binptr - rd_binptr_sync; + + always @(posedge wr_clk or negedge wr_nreset) + if (~wr_nreset) wr_full <= 1'b0; + else + wr_full <= (wr_chaosfull & wr_chaosmode) | + (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) == DEPTH; + + // Write --> Read clock synchronizer + for (i = 0; i < (AW + 1); i = i + 1) begin + la_drsync wrsync ( + .out(wr_grayptr_sync[i]), + .clk(rd_clk), + .nreset(rd_nreset), + .in(wr_grayptr[i]) + ); + end + + //########################### + //# READ SIDE LOGIC + //########################### + + always @(posedge rd_clk or negedge rd_nreset) + if (~rd_nreset) begin + rd_binptr_mem[AW:0] <= 'b0; + rd_binptr[AW:0] <= 'b0; + rd_grayptr[AW:0] <= 'b0; + end else begin + rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0]; + rd_binptr[AW:0] <= rd_binptr_nxt[AW:0]; + rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0]; + end + + assign rd_binptr_mem_nxt[AW:0] = rd_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (rd_en && ~rd_empty)}; + assign rd_binptr_nxt[AW:0] = rd_binptr[AW:0] + {{AW{1'b0}}, (rd_en && ~rd_empty)}; + assign rd_grayptr_nxt[AW:0] = rd_binptr_nxt[AW:0] ^ {1'b0, rd_binptr_nxt[AW:1]}; + + // Full comparison (gray pointer based) + always @(posedge rd_clk or negedge rd_nreset) + if (~rd_nreset) rd_empty <= 1'b1; + else rd_empty <= (rd_grayptr_nxt[AW:0] == wr_grayptr_sync[AW:0]); + + // Read --> write clock synchronizer + for (i = 0; i < (AW + 1); i = i + 1) begin + la_drsync rdsync ( + .out(rd_grayptr_sync[i]), + .clk(wr_clk), + .nreset(wr_nreset), + .in(rd_grayptr[i]) + ); + end + + //########################### + //# Dual Port Memory + //########################### + + reg [DW-1:0] ram[DEPTH-1:0]; + + // Write port (FIFO input) + always @(posedge wr_clk) if (wr_en & ~wr_full) ram[wr_binptr_mem[AW-1:0]] <= wr_din[DW-1:0]; + + // Read port (FIFO output) + assign rd_dout[DW-1:0] = ram[rd_binptr_mem[AW-1:0]]; + + //############################ + // Randomly Asserts FIFO full + //############################ + + generate + if (CHAOS) begin + // TODO: implement LFSR + reg chaosreg; + always @(posedge wr_clk or negedge wr_nreset) + if (~wr_nreset) chaosreg <= 1'b0; + else chaosreg <= ~chaosreg; + assign wr_chaosfull = chaosreg; + end else begin + assign wr_chaosfull = 1'b0; + end + + endgenerate + + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_dpram.v b/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_dpram.v new file mode 100644 index 00000000..129ef424 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_dpram.v @@ -0,0 +1,62 @@ +/***************************************************************************** + * Function: Dual Port RAM (One write port + One read port) + * Copyright: Lambda Project Authors. All rights Reserved. + * License: MIT (see LICENSE file in Lambda repository) + * + * Docs: + * + * This is a wrapper for selecting from a set of hardened memory macros. + * + * A synthesizable reference model is used when the TYPE is DEFAULT. The + * synthesizable model does not implement the cfg and test interface and should + * only be used for basic testing and for synthesizing for FPGA devices. + * Advanced ASIC development should rely on complete functional models + * supplied on a per macro basis. + * + * Technologoy specific implementations of "la_dpram" would generally include + * one ore more hardcoded instantiations of RAM modules with a generate + * statement relying on the "TYPE" to select between the list of modules + * at build time. + * + ****************************************************************************/ + +module la_dpram #( + parameter DW = 32, // Memory width + parameter AW = 10, // address width (derived) + parameter TYPE = "DEFAULT", // pass through variable for hard macro + parameter CTRLW = 128, // width of asic ctrl interface + parameter TESTW = 128 // width of asic test interface +) ( // Write port + input wr_clk, // write clock + input wr_ce, // write chip-enable + input wr_we, // write enable + input [DW-1:0] wr_wmask, // write mask + input [AW-1:0] wr_addr, // write address + input [DW-1:0] wr_din, //write data in + // Read port + input rd_clk, // read clock + input rd_ce, // read chip-enable + input [AW-1:0] rd_addr, // read address + output reg [DW-1:0] rd_dout, //read data out + // Power signal + input vss, // ground signal + input vdd, // memory core array power + input vddio, // periphery/io power + // Generic interfaces + input [CTRLW-1:0] ctrl, // pass through ASIC control interface + input [TESTW-1:0] test // pass through ASIC test interface +); + + // Generic RTL RAM + reg [DW-1:0] ram[(2**AW)-1:0]; + integer i; + + // Write port + always @(posedge wr_clk) + for (i = 0; i < DW; i = i + 1) + if (wr_ce & wr_we & wr_wmask[i]) ram[wr_addr[AW-1:0]][i] <= wr_din[i]; + + // Read Port + always @(posedge rd_clk) if (rd_ce) rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]]; + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_spram.v b/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_spram.v new file mode 100644 index 00000000..56635f1e --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_spram.v @@ -0,0 +1,245 @@ +/***************************************************************************** + * Function: Single Port ram + * Copyright: Lambda Project Authors. All rights Reserved. + * License: MIT (see LICENSE file in Lambda repository) + * + * Docs: + * + * This is a wrapper for selecting from a set of hardened memory macros. + * + * A synthesizable reference model is used when the TYPE is DEFAULT. The + * synthesizable model does not implement the cfg and test interface and should + * only be used for basic testing and for synthesizing for FPGA devices. + * Advanced ASIC development should rely on complete functional models + * supplied on a per macro basis. + * + * Technologoy specific implementations of "la_spram" would generally include + * one ore more hardcoded instantiations of ram modules with a generate + * statement relying on the "TYPE" to select between the list of modules + * at build time. + * + ****************************************************************************/ + +module la_spram + #(parameter DW = 32, // Memory width + parameter AW = 10, // Address width (derived) + parameter TYPE = "DEFAULT", // Pass through variable for hard macro + parameter CTRLW = 128, // Width of asic ctrl interface + parameter TESTW = 128 // Width of asic test interface + ) + (// Memory interface + input clk, // write clock + input ce, // chip enable + input we, // write enable + input [DW-1:0] wmask, //per bit write mask + input [AW-1:0] addr, //write address + input [DW-1:0] din, //write data + output [DW-1:0] dout, //read output data + // Power signals + input vss, // ground signal + input vdd, // memory core array power + input vddio, // periphery/io power + // Generic interfaces + input [CTRLW-1:0] ctrl, // pass through ASIC control interface + input [TESTW-1:0] test // pass through ASIC test interface + ); + + // Determine which memory to select + localparam MEM_TYPE = (TYPE != "DEFAULT") ? TYPE : + (AW >= 11) ? "RM_IHPSG13_1P_2048x64_c2_bm_bist" : + (AW == 10) ? "RM_IHPSG13_1P_1024x64_c2_bm_bist" : + (AW == 9) ? "RM_IHPSG13_1P_512x64_c2_bm_bist" : + (AW == 8) ? (DW >= 64) ? "RM_IHPSG13_1P_256x64_c2_bm_bist" : "RM_IHPSG13_1P_256x48_c2_bm_bist" : + "RM_IHPSG13_1P_64x64_c2_bm_bist"; + + localparam MEM_WIDTH = + (MEM_TYPE == "RM_IHPSG13_1P_1024x64_c2_bm_bist") ? 64 : + (MEM_TYPE == "RM_IHPSG13_1P_2048x64_c2_bm_bist") ? 64 : + (MEM_TYPE == "RM_IHPSG13_1P_256x48_c2_bm_bist") ? 48 : + (MEM_TYPE == "RM_IHPSG13_1P_256x64_c2_bm_bist") ? 64 : + (MEM_TYPE == "RM_IHPSG13_1P_512x64_c2_bm_bist") ? 64 : + (MEM_TYPE == "RM_IHPSG13_1P_64x64_c2_bm_bist") ? 64 : + 0; + + localparam MEM_DEPTH = + (MEM_TYPE == "RM_IHPSG13_1P_1024x64_c2_bm_bist") ? 10 : + (MEM_TYPE == "RM_IHPSG13_1P_2048x64_c2_bm_bist") ? 11 : + (MEM_TYPE == "RM_IHPSG13_1P_256x48_c2_bm_bist") ? 8 : + (MEM_TYPE == "RM_IHPSG13_1P_256x64_c2_bm_bist") ? 8 : + (MEM_TYPE == "RM_IHPSG13_1P_512x64_c2_bm_bist") ? 9 : + (MEM_TYPE == "RM_IHPSG13_1P_64x64_c2_bm_bist") ? 6 : + 0; + + // Create memories + localparam MEM_ADDRS = 2**(AW - MEM_DEPTH) < 1 ? 1 : 2**(AW - MEM_DEPTH); + + + + generate + genvar o; + for (o = 0; o < DW; o = o + 1) begin: OUTPUTS + wire [MEM_ADDRS-1:0] mem_outputs; + assign dout[o] = |mem_outputs; + end + + genvar a; + for (a = 0; a < MEM_ADDRS; a = a + 1) begin: ADDR + wire selected; + wire [MEM_DEPTH-1:0] mem_addr; + + if (MEM_ADDRS == 1) begin: FITS + assign selected = 1'b1; + assign mem_addr = addr; + end else begin: NOFITS + assign selected = addr[AW-1:MEM_DEPTH] == a; + assign mem_addr = addr[MEM_DEPTH-1:0]; + end + + genvar n; + for (n = 0; n < DW; n = n + MEM_WIDTH) begin: WORD + wire [MEM_WIDTH-1:0] mem_din; + wire [MEM_WIDTH-1:0] mem_dout; + wire [MEM_WIDTH-1:0] mem_wmask; + + genvar i; + for (i = 0; i < MEM_WIDTH; i = i + 1) begin: WORD_SELECT + if (n + i < DW) begin: ACTIVE + assign mem_din[i] = din[n + i]; + assign mem_wmask[i] = wmask[n + i]; + assign OUTPUTS[n + i].mem_outputs[a] = selected ? mem_dout[i] : 1'b0; + end + else begin: INACTIVE + assign mem_din[i] = 1'b0; + assign mem_wmask[i] = 1'b0; + end + end + + wire ce_in; + wire we_in; + assign ce_in = ce && selected; + assign we_in = we && selected; + + if (MEM_TYPE == "RM_IHPSG13_1P_1024x64_c2_bm_bist") + RM_IHPSG13_1P_1024x64_c2_bm_bist memory ( + .A_ADDR(mem_addr), + .A_BIST_ADDR('b0), + .A_BIST_BM('b0), + .A_BIST_CLK(1'b0), + .A_BIST_DIN('b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_WEN(1'b0), + .A_BM(mem_wmask), + .A_CLK(clk), + .A_DIN(mem_din), + .A_DLY(1'b1), + .A_DOUT(mem_dout), + .A_MEN(~ce_in), + .A_REN(we_in), + .A_WEN(~we_in) + ); + else if (MEM_TYPE == "RM_IHPSG13_1P_2048x64_c2_bm_bist") + RM_IHPSG13_1P_2048x64_c2_bm_bist memory ( + .A_ADDR(mem_addr), + .A_BIST_ADDR('b0), + .A_BIST_BM('b0), + .A_BIST_CLK(1'b0), + .A_BIST_DIN('b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_WEN(1'b0), + .A_BM(mem_wmask), + .A_CLK(clk), + .A_DIN(mem_din), + .A_DLY(1'b1), + .A_DOUT(mem_dout), + .A_MEN(~ce_in), + .A_REN(we_in), + .A_WEN(~we_in) + ); + else if (MEM_TYPE == "RM_IHPSG13_1P_256x48_c2_bm_bist") + RM_IHPSG13_1P_256x48_c2_bm_bist memory ( + .A_ADDR(mem_addr), + .A_BIST_ADDR('b0), + .A_BIST_BM('b0), + .A_BIST_CLK(1'b0), + .A_BIST_DIN('b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_WEN(1'b0), + .A_BM(mem_wmask), + .A_CLK(clk), + .A_DIN(mem_din), + .A_DLY(1'b1), + .A_DOUT(mem_dout), + .A_MEN(~ce_in), + .A_REN(we_in), + .A_WEN(~we_in) + ); + else if (MEM_TYPE == "RM_IHPSG13_1P_256x64_c2_bm_bist") + RM_IHPSG13_1P_256x64_c2_bm_bist memory ( + .A_ADDR(mem_addr), + .A_BIST_ADDR('b0), + .A_BIST_BM('b0), + .A_BIST_CLK(1'b0), + .A_BIST_DIN('b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_WEN(1'b0), + .A_BM(mem_wmask), + .A_CLK(clk), + .A_DIN(mem_din), + .A_DLY(1'b1), + .A_DOUT(mem_dout), + .A_MEN(~ce_in), + .A_REN(we_in), + .A_WEN(~we_in) + ); + else if (MEM_TYPE == "RM_IHPSG13_1P_512x64_c2_bm_bist") + RM_IHPSG13_1P_512x64_c2_bm_bist memory ( + .A_ADDR(mem_addr), + .A_BIST_ADDR('b0), + .A_BIST_BM('b0), + .A_BIST_CLK(1'b0), + .A_BIST_DIN('b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_WEN(1'b0), + .A_BM(mem_wmask), + .A_CLK(clk), + .A_DIN(mem_din), + .A_DLY(1'b1), + .A_DOUT(mem_dout), + .A_MEN(~ce_in), + .A_REN(we_in), + .A_WEN(~we_in) + ); + else if (MEM_TYPE == "RM_IHPSG13_1P_64x64_c2_bm_bist") + RM_IHPSG13_1P_64x64_c2_bm_bist memory ( + .A_ADDR(mem_addr), + .A_BIST_ADDR('b0), + .A_BIST_BM('b0), + .A_BIST_CLK(1'b0), + .A_BIST_DIN('b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_WEN(1'b0), + .A_BM(mem_wmask), + .A_CLK(clk), + .A_DIN(mem_din), + .A_DLY(1'b1), + .A_DOUT(mem_dout), + .A_MEN(~ce_in), + .A_REN(we_in), + .A_WEN(~we_in) + ); + end + end + endgenerate +endmodule \ No newline at end of file diff --git a/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_spregfile.v b/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_spregfile.v new file mode 100644 index 00000000..d167168c --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_spregfile.v @@ -0,0 +1,67 @@ +/***************************************************************************** + * Function: Single Port Register File + * Copyright: Lambda Project Authors. All rights Reserved. + * License: MIT (see LICENSE file in Lambda repository) + * + * Docs: + * + * This is a wrapper for selecting from a set of hardened register file macros. + * + * A synthesizable reference model is used when the TYPE is DEFAULT. The + * synthesizable model does not implement the cfg and test interface and should + * only be used for basic testing and for synthesizing for FPGA devices. + * Advanced ASIC development should rely on complete functional models + * supplied on a per macro basis. + * + * Technologoy specific implementations of "la_spregfile" would generally + * include one ore more hardcoded instantiations of RF modules with a generate + * statement relying on the "TYPE" to select between the list of modules + * at build time. + * + ****************************************************************************/ + +module la_spregfile #( + parameter DW = 32, // Memory width + parameter AW = 10, // Address width (derived) + parameter TYPE = "DEFAULT", // Pass through variable for hard macro + parameter CTRLW = 128, // Width of asic ctrl interface + parameter TESTW = 128 // Width of asic test interface +) ( // Memory interface + input clk, // write clock + input ce, // chip enable + input we, // write enable + input [ DW-1:0] wmask, //per bit write mask + input [ AW-1:0] addr, //write address + input [ DW-1:0] din, //write data + output [ DW-1:0] dout, //read output data + // Power signals + input vss, // ground signal + input vdd, // memory core array power + input vddio, // periphery/io power + // Generic interfaces + input [CTRLW-1:0] ctrl, // pass through ASIC control interface + input [TESTW-1:0] test // pass through ASIC test interface +); + + la_spram #( + .DW(DW), + .AW(AW), + .TYPE(TYPE), + .CTRLW(CTRLW), + .TESTW(TESTW) + ) memory ( + .clk(clk), + .ce(ce), + .we(we), + .wmask(wmask), + .addr(addr), + .din(din), + .dout(dout), + .vss(vss), + .vdd(vdd), + .vddio(vddio), + .ctrl(ctrl), + .test(test) + ); + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_syncfifo.v b/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_syncfifo.v new file mode 100644 index 00000000..6355a26d --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_syncfifo.v @@ -0,0 +1,120 @@ +/***************************************************************************** + * Function: Synchronous FIFO + * Copyright: Lambda Project Authors. All rights Reserved. + * License: MIT (see LICENSE file in Lambda repository) + * + * Docs: + * + * This is a wrapper for selecting from a set of hardened memory macros. + * + ****************************************************************************/ + +module la_syncfifo #( + parameter DW = 32, // Memory width + parameter DEPTH = 4, // FIFO depth + parameter NS = 1, // Number of power supplies + parameter CHAOS = 1, // generates random full logic when set + parameter CTRLW = 1, // width of asic ctrl interface + parameter TESTW = 1, // width of asic test interface + parameter TYPE = "DEFAULT" // Pass through variable for hard macro +) ( // common clock, reset, power, ctrl + input clk, + input nreset, + input vss, // ground signal + input [ NS-1:0] vdd, // supplies + input chaosmode, // randomly assert fifo full when set + input [CTRLW-1:0] ctrl, // pass through ASIC control interface + input [TESTW-1:0] test, // pass through ASIC test interface + // write input + input wr_en, // write fifo + input [ DW-1:0] wr_din, // data to write + output wr_full, // fifo full + // read output + input rd_en, // read fifo + output [ DW-1:0] rd_dout, // output data + output rd_empty // fifo is empty +); + + // local params + parameter AW = $clog2(DEPTH); + + // local wires + reg [AW:0] wr_addr; + wire [AW:0] wr_addr_nxt; + reg [AW:0] rd_addr; + wire [AW:0] rd_addr_nxt; + wire fifo_read; + wire fifo_write; + wire chaosfull; + wire rd_wrap_around; + wire wr_wrap_around; + + //############################ + // FIFO Empty/Full + //############################ + + // support any fifo depth + assign wr_full = (chaosfull & chaosmode) | {~wr_addr[AW], wr_addr[AW-1:0]} == rd_addr[AW:0]; + + assign rd_empty = wr_addr[AW:0] == rd_addr[AW:0]; + + assign fifo_read = rd_en & ~rd_empty; + + assign fifo_write = wr_en & ~wr_full; + + //############################ + // FIFO Pointers - wrap around DEPTH-1 + //############################ + assign rd_wrap_around = rd_addr[AW-1:0] == (DEPTH[AW-1:0] - 1'b1); + assign wr_wrap_around = wr_addr[AW-1:0] == (DEPTH[AW-1:0] - 1'b1); + + assign rd_addr_nxt[AW] = rd_wrap_around ? ~rd_addr[AW] : rd_addr[AW]; + assign rd_addr_nxt[AW-1:0] = rd_wrap_around ? 'b0 : (rd_addr[AW-1:0] + 1); + + assign wr_addr_nxt[AW] = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? ~wr_addr[AW] : wr_addr[AW]; + assign wr_addr_nxt[AW-1:0] = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? 'b0 : (wr_addr[AW-1:0] + 1); + + always @(posedge clk or negedge nreset) + if (~nreset) begin + wr_addr[AW:0] <= 'd0; + rd_addr[AW:0] <= 'b0; + end else if (fifo_write & fifo_read) begin + wr_addr[AW:0] <= wr_addr_nxt[AW:0]; + rd_addr[AW:0] <= rd_addr_nxt[AW:0]; + end else if (fifo_write) begin + wr_addr[AW:0] <= wr_addr_nxt[AW:0]; + end else if (fifo_read) begin + rd_addr[AW:0] <= rd_addr_nxt[AW:0]; + end + + //########################### + //# Dual Port Memory + //########################### + + reg [DW-1:0] ram[DEPTH-1:0]; + + // Write port (FIFO input) + always @(posedge clk) if (wr_en & ~wr_full) ram[wr_addr[AW-1:0]] <= wr_din[DW-1:0]; + + // Read port (FIFO output) + assign rd_dout[DW-1:0] = ram[rd_addr[AW-1:0]]; + + + //############################ + // Randomly Asserts FIFO full + //############################ + + generate + if (CHAOS) begin + // TODO: implement LFSR + reg chaosreg; + always @(posedge clk or negedge nreset) + if (~nreset) chaosreg <= 1'b0; + else chaosreg <= ~chaosreg; + assign chaosfull = chaosreg; + end else begin + assign chaosfull = 1'b0; + end + endgenerate + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_sram/pdngen.tcl b/lambdapdk/ihp130/libs/sg13g2_sram/pdngen.tcl new file mode 100644 index 00000000..844904ca --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_sram/pdngen.tcl @@ -0,0 +1,10 @@ +#################################### +# grid for: sky130sram +#################################### +define_pdn_grid -name {sg13g2_sram} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} \ + -halo {2.0 2.0 2.0 2.0} \ + -cells {RM_IHPSG13_1P_.*} +add_pdn_stripe -grid {sg13g2_sram} -layer {Metal5} -width {2.200} -pitch {22.0} -offset {11.0} +add_pdn_connect -grid {sg13g2_sram} -layers {Metal4 Metal5} +add_pdn_connect -grid {sg13g2_sram} -layers {Metal5 TopMetal1} diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell.py b/lambdapdk/ihp130/libs/sg13g2_stdcell.py new file mode 100644 index 00000000..9257228b --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell.py @@ -0,0 +1,135 @@ +import os +import siliconcompiler +from lambdapdk import register_data_source +from lambdapdk.ihp130 import register_ihp130_data_source + + +def setup(): + ''' + Nangate open standard cell library for FreePDK45. + ''' + libname = 'sg13g2_stdcell' + process = 'ihp130' + stackup = '5M2TL' + libtype = '9t' + version = 'r1p0' + + lib = siliconcompiler.Library(libname, package='ihp130') + register_ihp130_data_source(lib) + register_data_source(lib) + + libdir = os.path.join('lambdapdk', process, 'libs', libname) + + # version + lib.set('package', 'version', version) + + # list of stackups supported + lib.set('option', 'stackup', stackup) + + # list of pdks supported + lib.set('option', 'pdk', process) + + # footprint/type/sites + lib.set('asic', 'libarch', libtype) + lib.set('asic', 'site', libtype, 'CoreSite') + + # timing + lib.add('output', 'typ', 'nldm', + 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib') + lib.add('output', 'fast', 'nldm', + 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p32V_m40C.lib') + lib.add('output', 'slow', 'nldm', + 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p08V_125C.lib') + + # lef + lib.add('output', stackup, 'lef', + 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef') + + # gds + lib.add('output', stackup, 'gds', + 'ihp-sg13g2/libs.ref/sg13g2_stdcell/gds/sg13g2_stdcell.gds') + + # cdl + lib.add('output', stackup, 'cdl', + 'ihp-sg13g2/libs.ref/sg13g2_stdcell/cdl/sg13g2_stdcell.cdl') + + lib.add('output', 'rtl', 'verilog', + 'ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v') + + # clock buffers + lib.add('asic', 'cells', 'clkbuf', ["sg13g2_buf_2", + "sg13g2_buf_4"]) + + # tie cells + lib.add('asic', 'cells', 'tie', ["LOGIC1_X1", + "LOGIC0_X1"]) + + # hold cells + lib.add('asic', 'cells', 'hold', ["sg13g2_buf_1", + "sg13g2_buf_4"]) + + # filler + lib.add('asic', 'cells', 'filler', ["sg13g2_fill_1", + "sg13g2_fill_2"]) + + # decap + lib.add('asic', 'cells', 'decap', ["sg13g2_decap_4", + "sg13g2_decap_8"]) + + # antenna + lib.add('asic', 'cells', 'antenna', ["sg13g2_antennanp"]) + + # Stupid small cells + lib.add('asic', 'cells', 'dontuse', ["sg13g2_antennanp", + "sg13g2_lgcp_1", + "sg13g2_sighold", + "sg13g2_slgcp_1", + "sg13g2_dfrbp_2"]) + + # Techmap + lib.add('option', 'file', 'yosys_techmap', + libdir + '/techmap/yosys/cells_latch.v', + package='lambdapdk') + + # Defaults for OpenROAD tool variables + lib.set('option', 'var', 'openroad_place_density', '0.65') + lib.set('option', 'var', 'openroad_pad_global_place', '0') + lib.set('option', 'var', 'openroad_pad_detail_place', '0') + lib.set('option', 'var', 'openroad_macro_place_halo', ['40', '40']) + lib.set('option', 'var', 'openroad_macro_place_channel', ['80', '80']) + + lib.set('option', 'file', 'openroad_tapcells', libdir + '/apr/openroad/tapcell.tcl', + package='lambdapdk') + lib.set('option', 'file', 'openroad_pdngen', libdir + '/apr/openroad/pdngen.tcl', + package='lambdapdk') + lib.set('option', 'file', 'openroad_global_connect', + libdir + '/apr/openroad/global_connect.tcl', + package='lambdapdk') + + lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000") # convert from ns -> ps + lib.set('option', 'var', 'yosys_abc_constraint_load', "6.0fF") # BUF_X1 = 0.974659 x 4 + lib.set('option', 'var', 'yosys_driver_cell', "sg13g2_buf_4") + lib.set('option', 'var', 'yosys_buffer_cell', "sg13g2_buf_4") + lib.set('option', 'var', 'yosys_buffer_input', "A") + lib.set('option', 'var', 'yosys_buffer_output', "X") + for tool in ('yosys', 'openroad'): + lib.set('option', 'var', f'{tool}_tiehigh_cell', "sg13g2_tiehi") + lib.set('option', 'var', f'{tool}_tiehigh_port', "L_HI") + lib.set('option', 'var', f'{tool}_tielow_cell', "sg13g2_tielo") + lib.set('option', 'var', f'{tool}_tielow_port', "L_LO") + + libs = [lib] + for libtype in ('stdlib', 'auxlib'): + lambda_lib = siliconcompiler.Library(f'lambdalib_{libtype}_{libname}', + package='lambdapdk') + register_data_source(lambda_lib) + lambda_lib.add('option', 'ydir', libdir + f'/lambda/{libtype}') + libs.append(lambda_lib) + + return libs + + +######################### +if __name__ == "__main__": + lib = setup(siliconcompiler.Chip('')) + lib.write_manifest(f'{lib.top()}.json') diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/apr/openroad/global_connect.tcl b/lambdapdk/ihp130/libs/sg13g2_stdcell/apr/openroad/global_connect.tcl new file mode 100644 index 00000000..2f13fdb2 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/apr/openroad/global_connect.tcl @@ -0,0 +1,8 @@ +#################################### +# global connections +#################################### +add_global_connection -net {VDD} -pin_pattern {^VDD$} -power +add_global_connection -net {VDD} -pin_pattern {^VDDPE$} +add_global_connection -net {VDD} -pin_pattern {^VDDCE$} +add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground +add_global_connection -net {VSS} -pin_pattern {^VSSE$} diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/apr/openroad/pdngen.tcl b/lambdapdk/ihp130/libs/sg13g2_stdcell/apr/openroad/pdngen.tcl new file mode 100644 index 00000000..b46a5d65 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/apr/openroad/pdngen.tcl @@ -0,0 +1,24 @@ +#################################### +# voltage domains +#################################### +set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} +##################################### +# standard cell grid +#################################### +define_pdn_grid -name {grid} -voltage_domains {CORE} +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -followpins +set met5_pitch [expr {([lindex [ord::get_core_area] 3] - [lindex [ord::get_core_area] 1]) / 2}] +if {$met5_pitch > 75.6} { + set met5_pitch 75.6 +} +add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch $met5_pitch \ + -offset [expr {$met5_pitch / 2}] +set top1_pitch [expr {([lindex [ord::get_core_area] 2] - [lindex [ord::get_core_area] 0]) / 2}] +if {$top1_pitch > 75.6} { + set top1_pitch 75.6 +} +add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch $met5_pitch \ + -offset [expr {$met5_pitch / 2}] +add_pdn_connect -grid {grid} -layers {Metal1 Metal5} +add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} +#################################### diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/apr/openroad/tapcell.tcl b/lambdapdk/ihp130/libs/sg13g2_stdcell/apr/openroad/tapcell.tcl new file mode 100644 index 00000000..2872324c --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/apr/openroad/tapcell.tcl @@ -0,0 +1 @@ +cut_rows diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_antenna.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_antenna.v new file mode 100644 index 00000000..d4763384 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_antenna.v @@ -0,0 +1,19 @@ +//############################################################################# +//# Function: Antenna Diode # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_antenna #( + parameter PROP = "DEFAULT" +) ( + input vss, + output z +); + + sg13g2_antennanp u0 ( + .A (z), + .VSS(vss) + ); + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkicgand.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkicgand.v new file mode 100644 index 00000000..64ddcf27 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkicgand.v @@ -0,0 +1,28 @@ +//############################################################################# +//# Function: Integrated "And" Clock Gating Cell (And) # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_clkicgand #( + parameter PROP = "DEFAULT" +) ( + input clk, // clock input + input te, // test enable + input en, // enable (from positive edge FF) + output eclk // enabled clock output +); + + // reg en_stable; + + // always @(clk or en or te) if (~clk) en_stable <= en | te; + + // assign eclk = clk & en_stable; + + sg13g2_lgcp_1 u0 ( + .CLK (clk), + .GATE(en), + .GCLK(eclk) + ); + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkicgor.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkicgor.v new file mode 100644 index 00000000..e523157c --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkicgor.v @@ -0,0 +1,42 @@ +//############################################################################# +//# Function: Integrated "Or" Clock Gating Cell # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_clkicgor #( + parameter PROP = "DEFAULT" +) ( + input clk, // clock input + input te, // test enable + input en, // enable + output eclk // enabled clock output +); + + // reg en_stable; + + // always @(clk or en or te) if (clk) en_stable <= en | te; + + // assign eclk = clk | ~en_stable; + + wire eclk_int; + wire en_bar; + + sg13g2_lgcp_1 u0 ( + .CLK (clk), + .GATE(en), + .GCLK(eclk_int) + ); + + sg13g2_inv_1 u1 ( + .A(en), + .Y(en_bar) + ); + sg13g2_or2_1 u2 ( + .A(en_bar), + .B(eclk_int), + .X(eclk) + ); + + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkmux2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkmux2.v new file mode 100644 index 00000000..a3f2dae3 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkmux2.v @@ -0,0 +1,71 @@ +//############################################################################# +//# Function: 2-Input Glitch-Free Clock Mux # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_clkmux2 #( + parameter PROP = "DEFAULT" // cell property +) ( + input clk0, + input clk1, + input sel0, + input sel1, + input nreset, + output out +); + + wire [1:0] maskb; + wire [1:0] en; + wire enb; + wire [1:0] ensync; + wire ensyncb; + wire [1:0] clkg; + + // invert mask (2) + la_inv iinv[1:0] ( + .a({ensync[0], ensync[1]}), + .z(maskb[1:0]) + ); + + // clock enable (2) + la_and2 isel[1:0] ( + .a({sel1, sel0}), + .b(maskb[1:0]), + .z(en[1:0]) + ); + + la_inv ienb ( + .a(en[0]), + .z(enb) + ); + + // synchronizers (2) + la_drsync isync[1:0] ( + .clk({clk1, clk0}), + .nreset({nreset, nreset}), + .in({en[1], enb}), + .out({ensync[1], ensyncb}) + ); + + la_inv iensync ( + .a(ensyncb), + .z(ensync[0]) + ); + + // glith free clock gate (2) + la_clkicgand igate[1:0] ( + .clk ({clk1, clk0}), + .te (2'b00), + .en (ensync[1:0]), + .eclk(clkg[1:0]) + ); + + // final clock or (1) + la_clkor2 iorclk ( + .a(clkg[0]), + .b(clkg[1]), + .z(out) + ); + +endmodule // la_clkmux2 diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkmux4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkmux4.v new file mode 100644 index 00000000..62021ae6 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_clkmux4.v @@ -0,0 +1,105 @@ +//############################################################################# +//# Function: 4-Input Glitch-Free Clock Mux # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_clkmux4 #( + parameter PROP = "DEFAULT" // cell property +) ( + input clk0, + input clk1, + input clk2, + input clk3, + input sel0, + input sel1, + input sel2, + input sel3, + input nreset, + output out +); + + wire [3:0] mask; + wire [3:0] maskb; + wire [3:0] en; + wire enb; + wire [3:0] ensync; + wire ensyncb; + wire [3:0] clkg; + wire [3:0] nreset_sync; + + // create clock mask (4) + la_or3 ior0 ( + .a(ensync[3]), + .b(ensync[2]), + .c(ensync[1]), + .z(mask[0]) + ); + la_or3 ior1 ( + .a(ensync[0]), + .b(ensync[3]), + .c(ensync[2]), + .z(mask[1]) + ); + la_or3 ior2 ( + .a(ensync[1]), + .b(ensync[0]), + .c(ensync[3]), + .z(mask[2]) + ); + la_or3 ior3 ( + .a(ensync[2]), + .b(ensync[1]), + .c(ensync[0]), + .z(mask[3]) + ); + + // invert mask (4) + la_inv iinv[3:0] ( + .a(mask[3:0]), + .z(maskb[3:0]) + ); + + // clock enable (4) + la_and2 isel[3:0] ( + .a({sel3, sel2, sel1, sel0}), + .b(maskb[3:0]), + .z(en[3:0]) + ); + + la_inv ienb ( + .a(en[0]), + .z(enb) + ); + + // data synchronizer with reset (since clocks aren't guaranteed) + la_drsync idrsync[3:0] ( + .clk({clk3, clk2, clk1, clk0}), + .nreset({4{nreset}}), + .in({en[3:1], enb}), + .out({ensync[3:1], ensyncb}) + ); + + la_inv iensync ( + .a(ensyncb), + .z(ensync[0]) + ); + + // glith free clock gate (4) + la_clkicgand igate[3:0] ( + .clk ({clk3, clk2, clk1, clk0}), + .te (4'b0000), + .en (ensync[3:0]), + .eclk(clkg[3:0]) + ); + + // final clock or (1) + la_clkor4 iorclk ( + .a(clkg[0]), + .b(clkg[1]), + .c(clkg[2]), + .d(clkg[3]), + .z(out) + ); + +endmodule // la_clkmux4 diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_drsync.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_drsync.v new file mode 100644 index 00000000..8bebc7cb --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_drsync.v @@ -0,0 +1,25 @@ +//############################################################################# +//# Function: Synchronizer with async reset # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# +module la_drsync #( + parameter PROP = "DEFAULT" +) ( + input clk, // clock + input in, // input data + input nreset, // async active low reset + output out // synchronized data +); + + localparam STAGES = 2; + + reg [STAGES-1:0] shiftreg; + + always @(posedge clk or negedge nreset) + if (!nreset) shiftreg[STAGES-1:0] <= 'b0; + else shiftreg[STAGES-1:0] <= {shiftreg[STAGES-2:0], in}; + + assign out = shiftreg[STAGES-1]; + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_dsync.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_dsync.v new file mode 100644 index 00000000..67740059 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_dsync.v @@ -0,0 +1,53 @@ +//############################################################################# +//# Function: Synchronizer # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# +module la_dsync #( + parameter PROP = "DEFAULT", + parameter STAGES = 2, // synchronizer depth + parameter RND = 1 +) // randomize simulation delay +( + input clk, // clock + input in, // input data + output out // synchronized data +); + + // reg [STAGES:0] shiftreg; + // always @(posedge clk) + // shiftreg[STAGES:0] <= {shiftreg[STAGES-1:0], in}; + + // `ifdef SIM + // integer sync_delay; + // always @(posedge clk) + // sync_delay <= {$random} % 2; + // assign out = (|sync_delay & (|RND)) ? shiftreg[STAGES] : shiftreg[STAGES-1]; + // `else + // assign out = shiftreg[STAGES-1]; + // `endif + + genvar i; + generate + for (i = 0; i < STAGES; i = i + 1) begin : DELAY + wire reg_in; + wire reg_out; + if (i == 0) begin : SEL_IN + assign reg_in = in; + end else begin : SEL_PREV + assign reg_in = reg_out[i-1]; + end + + sg13g2_dfrbp_1 u0 ( + .CLK(clk), + .D(reg_in), + .Q(reg_out), + .QN(), + .RESET_B(1'b1) + ); + end + endgenerate + + assign out = DELAY[STAGES-1].reg_out; + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_iddr.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_iddr.v new file mode 100644 index 00000000..c3970d7d --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_iddr.v @@ -0,0 +1,26 @@ +//############################################################################# +//# Function: Dual data rate input buffer # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_iddr #( + parameter PROP = "DEFAULT" +) ( + input clk, // clock + input in, // data input sampled on both edges of clock + output reg outrise, // rising edge sample + output reg outfall // falling edge sample +); + + // Negedge Sample + always @(negedge clk) outfall <= in; + + // Posedge Sample + reg inrise; + always @(posedge clk) inrise <= in; + + // Posedge Latch (for hold) + always @(clk or inrise) if (~clk) outrise <= inrise; + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_isohi.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_isohi.v new file mode 100644 index 00000000..0b60b3ef --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_isohi.v @@ -0,0 +1,17 @@ +//############################################################################# +//# Function: Power isolation circuit # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_isohi #( + parameter PROP = "DEFAULT" +) ( + input iso, // isolation signal + input in, // input + output out // out = iso | in +); + + assign out = iso | in; + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_isolo.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_isolo.v new file mode 100644 index 00000000..e8ca1cb6 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_isolo.v @@ -0,0 +1,17 @@ +//############################################################################# +//# Function: Power isolation circuit # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_isolo #( + parameter PROP = "DEFAULT" +) ( + input iso, // isolation signal + input in, // input + output out // out = ~iso & in +); + + assign out = ~iso & in; + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_oddr.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_oddr.v new file mode 100644 index 00000000..bda1d2d9 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_oddr.v @@ -0,0 +1,23 @@ +//############################################################################# +//# Function: Dual data rate output buffer # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_oddr #( + parameter PROP = "DEFAULT" +) ( + input clk, // clock input + input in0, // data for clk=0 + input in1, // data for clk=1 + output out // dual data rate output +); + + //Making in1 stable for clk=1 + reg in1_sh; + always @(clk or in1) if (~clk) in1_sh <= in1; + + //Using clock as data selector + assign out = clk ? in1_sh : in0; + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_pwrbuf.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_pwrbuf.v new file mode 100644 index 00000000..9621f942 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_pwrbuf.v @@ -0,0 +1,23 @@ +//############################################################################# +//# Function: Non-inverting buffer with supplies # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_pwrbuf #( + parameter PROP = "DEFAULT" +) ( + input vdd, + input vss, + input a, + output z +); + + sg13g2_buf_1 u0 ( + .A (a), + .X (z), + .VSS(vss), + .VDD(vdd) + ); + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_rsync.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_rsync.v new file mode 100644 index 00000000..943e3b10 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_rsync.v @@ -0,0 +1,60 @@ +//############################################################################# +//# Function: Reset synchronizer (async assert, sync deassert) # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# +module la_rsync #( + parameter PROP = "DEFAULT", + parameter STAGES = 2, // synchronizer depth + parameter RND = 1 +) // randomize sync + +( + input clk, // clock + input nrst_in, // async reset input + output nrst_out // async assert, sync deassert reset +); + + // reg [STAGES:0] sync_pipe; + // integer sync_delay; + + + // always @(posedge clk or negedge nrst_in) + // if (!nrst_in) + // sync_pipe[STAGES:0] <= 'b0; + // else + // sync_pipe[STAGES:0] <= {sync_pipe[STAGES-1:0], 1'b1}; + + // `ifdef SIM + // always @(posedge clk) + // sync_delay <= {$random} % 2; + + // assign nrst_out = (|sync_delay & (|RND)) ? sync_pipe[STAGES] : sync_pipe[STAGES-1]; + // `else + // assign nrst_out = sync_pipe[STAGES-1]; + // `endif + + genvar i; + generate + for (i = 0; i < STAGES; i = i + 1) begin : DELAY + wire reg_in; + wire reg_out; + if (i == 0) begin : SEL_IN + LOGIC1_X1 u1 (.Z(reg_in)); + end else begin : SEL_PREV + assign reg_in = reg_out[i-1]; + end + + sg13g2_dfrbp_1 u0 ( + .CLK(clk), + .D(reg_in), + .Q(reg_out), + .QN(), + .RESET_B(nrest_in) + ); + end + endgenerate + + assign nrst_out = DELAY[STAGES-1].reg_out; + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_tbuf.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_tbuf.v new file mode 100644 index 00000000..820baf41 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/auxlib/la_tbuf.v @@ -0,0 +1,23 @@ +//############################################################################# +//# Function: Tristate Buffer # +//# Copyright: Lambda Project Authors. All rights Reserved. # +//# License: MIT (see LICENSE file in Lambda repository) # +//############################################################################# + +module la_tbuf #( + parameter PROP = "DEFAULT" +) ( + input a, + input oe, + output z +); + + // assign z = oe ? a : 1'bz; + + sg13g2_ebufn_2 u0 ( + .A(a), + .TE_B(~oe), + .Z(z) + ); + +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_and2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_and2.v new file mode 100644 index 00000000..8cbc581b --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_and2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2-Input AND Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_and2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = a & b; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_and2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_and2_1 _0_ ( + .A(b), + .B(a), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_and3.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_and3.v new file mode 100644 index 00000000..08161679 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_and3.v @@ -0,0 +1,37 @@ +// //############################################################################# +// //# Function: 3-Input AND Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_and3 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// output z +// ); +// +// assign z = a & b & c; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_and3(a, b, c, z); + input a; + wire a; + input b; + wire b; + input c; + wire c; + output z; + wire z; + sg13g2_and3_1 _0_ ( + .A(b), + .B(a), + .C(c), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_and4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_and4.v new file mode 100644 index 00000000..b13f62ff --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_and4.v @@ -0,0 +1,41 @@ +// //############################################################################# +// //# Function: 4-Input AND Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_and4 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// input d, +// output z +// ); +// +// assign z = a & b & c & d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_and4(a, b, c, d, z); + input a; + wire a; + input b; + wire b; + input c; + wire c; + input d; + wire d; + output z; + wire z; + sg13g2_and4_1 _0_ ( + .A(b), + .B(a), + .C(c), + .D(d), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao21.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao21.v new file mode 100644 index 00000000..f90b0b2b --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao21.v @@ -0,0 +1,37 @@ +// //############################################################################# +// //# Function: And-Or (ao21) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_ao21 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// output z +// ); +// +// assign z = (a0 & a1) | b0; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_ao21(a0, a1, b0, z); + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + output z; + wire z; + sg13g2_a21o_1 _0_ ( + .A1(a1), + .A2(a0), + .B1(b0), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao211.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao211.v new file mode 100644 index 00000000..576c0327 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao211.v @@ -0,0 +1,46 @@ +// //############################################################################# +// //# Function: And-Or (ao211) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_ao211 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input c0, +// output z +// ); +// +// assign z = (a0 & a1) | b0 | c0; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_ao211(a0, a1, b0, c0, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input c0; + wire c0; + output z; + wire z; + sg13g2_a21oi_2 _1_ ( + .A1(a1), + .A2(a0), + .B1(b0), + .Y(_0_) + ); + sg13g2_nand2b_2 _2_ ( + .A_N(c0), + .B(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao22.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao22.v new file mode 100644 index 00000000..9a755eb6 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao22.v @@ -0,0 +1,46 @@ +// //############################################################################# +// //# Function: And-Or (ao22) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_ao22 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// output z +// ); +// +// assign z = (a0 & a1) | (b0 & b1); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_ao22(a0, a1, b0, b1, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + output z; + wire z; + sg13g2_a22oi_1 _1_ ( + .A1(a1), + .A2(a0), + .B1(b1), + .B2(b0), + .Y(_0_) + ); + sg13g2_inv_1 _2_ ( + .A(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao221.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao221.v new file mode 100644 index 00000000..45f70b7d --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao221.v @@ -0,0 +1,50 @@ +// //############################################################################# +// //# Function: And-Or (ao221) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_ao221 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// input c0, +// output z +// ); +// +// assign z = (a0 & a1) | (b0 & b1) | (c0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_ao221(a0, a1, b0, b1, c0, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + input c0; + wire c0; + output z; + wire z; + sg13g2_a221oi_1 _1_ ( + .A1(a1), + .A2(a0), + .B1(b1), + .B2(b0), + .C1(c0), + .Y(_0_) + ); + sg13g2_inv_1 _2_ ( + .A(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao222.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao222.v new file mode 100644 index 00000000..c8dcd80d --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao222.v @@ -0,0 +1,59 @@ +// //############################################################################# +// //# Function: And-Or (ao222) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_ao222 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// input c0, +// input c1, +// output z +// ); +// +// assign z = (a0 & a1) | (b0 & b1) | (c0 & c1); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_ao222(a0, a1, b0, b1, c0, c1, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + input c0; + wire c0; + input c1; + wire c1; + output z; + wire z; + sg13g2_nand2_1 _2_ ( + .A(b1), + .B(b0), + .Y(_0_) + ); + sg13g2_a22oi_1 _3_ ( + .A1(c1), + .A2(c0), + .B1(a1), + .B2(a0), + .Y(_1_) + ); + sg13g2_nand2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao31.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao31.v new file mode 100644 index 00000000..c28bcbda --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao31.v @@ -0,0 +1,46 @@ +// //############################################################################# +// //# Function: And-Or (ao31) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_ao31 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// output z +// ); +// +// assign z = (a0 & a1 & a2) | b0; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_ao31(a0, a1, a2, b0, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + output z; + wire z; + sg13g2_nand3_1 _1_ ( + .A(a1), + .B(a0), + .C(a2), + .Y(_0_) + ); + sg13g2_nand2b_2 _2_ ( + .A_N(b0), + .B(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao311.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao311.v new file mode 100644 index 00000000..32b9b714 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao311.v @@ -0,0 +1,55 @@ +// //############################################################################# +// //# Function: And-Or (ao311) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_ao311 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input c0, +// output z +// ); +// +// assign z = (a0 & a1 & a2) | b0 | c0; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_ao311(a0, a1, a2, b0, c0, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input c0; + wire c0; + output z; + wire z; + sg13g2_nand3_1 _2_ ( + .A(a1), + .B(a0), + .C(a2), + .Y(_0_) + ); + sg13g2_nor2_2 _3_ ( + .A(b0), + .B(c0), + .Y(_1_) + ); + sg13g2_nand2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao32.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao32.v new file mode 100644 index 00000000..0c09dc98 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao32.v @@ -0,0 +1,55 @@ +// //############################################################################# +// //# Function: And-Or (ao32) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_ao32 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input b1, +// output z +// ); +// +// assign z = (a0 & a1 & a2) | (b0 & b1); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_ao32(a0, a1, a2, b0, b1, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input b1; + wire b1; + output z; + wire z; + sg13g2_nand2_1 _2_ ( + .A(b1), + .B(b0), + .Y(_0_) + ); + sg13g2_nand3_1 _3_ ( + .A(a1), + .B(a0), + .C(a2), + .Y(_1_) + ); + sg13g2_nand2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao33.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao33.v new file mode 100644 index 00000000..e8cb8be5 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_ao33.v @@ -0,0 +1,59 @@ +// //############################################################################# +// //# Function: And-Or (ao33) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_ao33 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input b1, +// input b2, +// output z +// ); +// +// assign z = (a0 & a1 & a2) | (b0 & b1 & b2); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_ao33(a0, a1, a2, b0, b1, b2, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input b1; + wire b1; + input b2; + wire b2; + output z; + wire z; + sg13g2_nand3_1 _2_ ( + .A(b2), + .B(b1), + .C(b0), + .Y(_0_) + ); + sg13g2_nand3_1 _3_ ( + .A(a1), + .B(a0), + .C(a2), + .Y(_1_) + ); + sg13g2_nand2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi21.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi21.v new file mode 100644 index 00000000..dbedfc7e --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi21.v @@ -0,0 +1,37 @@ +// //############################################################################# +// //# Function: And-Or-Inverter (aoi21) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_aoi21 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// output z +// ); +// +// assign z = ~((a0 & a1) | b0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_aoi21(a0, a1, b0, z); + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + output z; + wire z; + sg13g2_a21oi_2 _0_ ( + .A1(a1), + .A2(a0), + .B1(b0), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi211.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi211.v new file mode 100644 index 00000000..9895575c --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi211.v @@ -0,0 +1,46 @@ +// //############################################################################# +// //# Function: And-Or-Inverter (aoi211) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_aoi211 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input c0, +// output z +// ); +// +// assign z = ~((a0 & a1) | b0 | c0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_aoi211(a0, a1, b0, c0, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input c0; + wire c0; + output z; + wire z; + sg13g2_a21oi_2 _1_ ( + .A1(a1), + .A2(a0), + .B1(b0), + .Y(_0_) + ); + sg13g2_nor2b_1 _2_ ( + .A(c0), + .B_N(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi22.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi22.v new file mode 100644 index 00000000..5bd7d177 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi22.v @@ -0,0 +1,41 @@ +// //############################################################################# +// //# Function: And-Or-Inverter (aoi22) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_aoi22 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// output z +// ); +// +// assign z = ~((a0 & a1) | (b0 & b1)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_aoi22(a0, a1, b0, b1, z); + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + output z; + wire z; + sg13g2_a22oi_1 _0_ ( + .A1(a1), + .A2(a0), + .B1(b1), + .B2(b0), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi221.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi221.v new file mode 100644 index 00000000..dc0ba866 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi221.v @@ -0,0 +1,45 @@ +// //############################################################################# +// //# Function: And-Or-Inverter (aoi221) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_aoi221 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// input c0, +// output z +// ); +// +// assign z = ~((a0 & a1) | (b0 & b1) | c0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_aoi221(a0, a1, b0, b1, c0, z); + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + input c0; + wire c0; + output z; + wire z; + sg13g2_a221oi_1 _0_ ( + .A1(a1), + .A2(a0), + .B1(b1), + .B2(b0), + .C1(c0), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi222.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi222.v new file mode 100644 index 00000000..6418fb29 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi222.v @@ -0,0 +1,54 @@ +// //############################################################################# +// //# Function: And-Or-Inverter (aoi222) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_aoi222 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// input c0, +// input c1, +// output z +// ); +// +// assign z = ~((a0 & a1) | (b0 & b1) | (c0 & c1)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_aoi222(a0, a1, b0, b1, c0, c1, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + input c0; + wire c0; + input c1; + wire c1; + output z; + wire z; + sg13g2_and2_1 _1_ ( + .A(b1), + .B(b0), + .X(_0_) + ); + sg13g2_a221oi_1 _2_ ( + .A1(c1), + .A2(c0), + .B1(a1), + .B2(a0), + .C1(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi31.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi31.v new file mode 100644 index 00000000..109c00fa --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi31.v @@ -0,0 +1,46 @@ +// //############################################################################# +// //# Function: And-Or-Inverter (aoi31) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_aoi31 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// output z +// ); +// +// assign z = ~((a0 & a1 & a2) | b0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_aoi31(a0, a1, a2, b0, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + output z; + wire z; + sg13g2_nand3_1 _1_ ( + .A(a1), + .B(a0), + .C(a2), + .Y(_0_) + ); + sg13g2_nor2b_1 _2_ ( + .A(b0), + .B_N(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi311.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi311.v new file mode 100644 index 00000000..c67283c2 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi311.v @@ -0,0 +1,50 @@ +// //############################################################################# +// //# Function: And-Or-Inverter (aoi311) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_aoi311 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input c0, +// output z +// ); +// +// assign z = ~((a0 & a1 & a2) | b0 | c0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_aoi311(a0, a1, a2, b0, c0, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input c0; + wire c0; + output z; + wire z; + sg13g2_and3_1 _1_ ( + .A(a1), + .B(a0), + .C(a2), + .X(_0_) + ); + sg13g2_nor3_2 _2_ ( + .A(c0), + .B(b0), + .C(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi32.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi32.v new file mode 100644 index 00000000..82fd4ec9 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi32.v @@ -0,0 +1,50 @@ +// //############################################################################# +// //# Function: And-Or-Inverter (aoi32) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_aoi32 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input b1, +// output z +// ); +// +// assign z = ~((a0 & a1 & a2) | (b0 & b1)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_aoi32(a0, a1, a2, b0, b1, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input b1; + wire b1; + output z; + wire z; + sg13g2_and2_1 _1_ ( + .A(a0), + .B(a2), + .X(_0_) + ); + sg13g2_a22oi_1 _2_ ( + .A1(b1), + .A2(b0), + .B1(_0_), + .B2(a1), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi33.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi33.v new file mode 100644 index 00000000..ac1c4f9b --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_aoi33.v @@ -0,0 +1,59 @@ +// //############################################################################# +// //# Function: And-Or-Inverter (aoi33) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_aoi33 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input b1, +// input b2, +// output z +// ); +// +// assign z = ~((a0 & a1 & a2) | (b0 & b1 & b2)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_aoi33(a0, a1, a2, b0, b1, b2, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input b1; + wire b1; + input b2; + wire b2; + output z; + wire z; + sg13g2_nand3_1 _2_ ( + .A(a2), + .B(a1), + .C(a0), + .Y(_0_) + ); + sg13g2_nand3_1 _3_ ( + .A(b1), + .B(b0), + .C(b2), + .Y(_1_) + ); + sg13g2_and2_1 _4_ ( + .A(_0_), + .B(_1_), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_buf.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_buf.v new file mode 100644 index 00000000..89d33712 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_buf.v @@ -0,0 +1,26 @@ +// //############################################################################# +// //# Function: Non-inverting Buffer # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_buf #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// output z +// ); +// +// assign z = a; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_buf(a, z); + input a; + wire a; + output z; + wire z; + assign z = a; +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkand2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkand2.v new file mode 100644 index 00000000..d8774cde --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkand2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2 Input Clock And Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_clkand2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = a & b; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_clkand2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_and2_1 _0_ ( + .A(b), + .B(a), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkbuf.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkbuf.v new file mode 100644 index 00000000..a34e5b20 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkbuf.v @@ -0,0 +1,26 @@ +// //############################################################################# +// //# Function: Non-inverting Clock Buffer # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_clkbuf #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// output z +// ); +// +// assign z = a; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_clkbuf(a, z); + input a; + wire a; + output z; + wire z; + assign z = a; +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkinv.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkinv.v new file mode 100644 index 00000000..7eb481e5 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkinv.v @@ -0,0 +1,29 @@ +// //############################################################################# +// //# Function: Clock Inverter # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_clkinv #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// output z +// ); +// +// assign z = ~a; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_clkinv(a, z); + input a; + wire a; + output z; + wire z; + sg13g2_inv_2 _0_ ( + .A(a), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clknand2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clknand2.v new file mode 100644 index 00000000..f96c67bd --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clknand2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2 Input Clock Nand Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_clknand2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = ~(a & b); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_clknand2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_nand2_2 _0_ ( + .A(b), + .B(a), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clknor2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clknor2.v new file mode 100644 index 00000000..ef130fd6 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clknor2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2-Input Clock NOR Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_clknor2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = ~(a | b); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_clknor2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_nor2_2 _0_ ( + .A(b), + .B(a), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkor2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkor2.v new file mode 100644 index 00000000..da211f3d --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkor2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2-Input Clock OR Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_clkor2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = a | b; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_clkor2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_or2_1 _0_ ( + .A(b), + .B(a), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkor4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkor4.v new file mode 100644 index 00000000..f58359a3 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkor4.v @@ -0,0 +1,41 @@ +// //############################################################################# +// //# Function: 4 Input Clock Or Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_clkor4 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// input d, +// output z +// ); +// +// assign z = a | b | c | d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_clkor4(a, b, c, d, z); + input a; + wire a; + input b; + wire b; + input c; + wire c; + input d; + wire d; + output z; + wire z; + sg13g2_or4_1 _0_ ( + .A(b), + .B(a), + .C(c), + .D(d), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkxor2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkxor2.v new file mode 100644 index 00000000..f625a6b2 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_clkxor2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2-Input Clock XOR Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_clkxor2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = a ^ b; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_clkxor2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_xor2_1 _0_ ( + .A(b), + .B(a), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_csa32.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_csa32.v new file mode 100644 index 00000000..d17c73b0 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_csa32.v @@ -0,0 +1,64 @@ +// //############################################################################# +// //# Function: Carry Save Adder (3:2) # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_csa32 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// output sum, +// output carry +// ); +// +// assign sum = a ^ b ^ c; +// assign carry = (a & b) | (b & c) | (c & a); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_csa32(a, b, c, sum, carry); + wire _0_; + wire _1_; + wire _2_; + input a; + wire a; + input b; + wire b; + input c; + wire c; + output carry; + wire carry; + output sum; + wire sum; + sg13g2_xnor2_1 _3_ ( + .A(b), + .B(c), + .Y(_0_) + ); + sg13g2_xnor2_1 _4_ ( + .A(a), + .B(_0_), + .Y(sum) + ); + sg13g2_nand2_1 _5_ ( + .A(b), + .B(c), + .Y(_1_) + ); + sg13g2_o21ai_1 _6_ ( + .A1(b), + .A2(c), + .B1(a), + .Y(_2_) + ); + sg13g2_nand2_1 _7_ ( + .A(_1_), + .B(_2_), + .Y(carry) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_csa42.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_csa42.v new file mode 100644 index 00000000..9be3e2e6 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_csa42.v @@ -0,0 +1,114 @@ +// //############################################################################# +// //# Function: Carry Save Adder (4:2) (aka 5:3) # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_csa42 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// input d, +// input cin, +// output sum, +// output carry, +// output cout +// ); +// +// assign cout = (a & b) | (b & c) | (a & c); +// assign sumint = a ^ b ^ c; +// assign sum = cin ^ d ^ sumint; +// assign carry = (cin & d) | (cin & sumint) | (d & sumint); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_csa42(a, b, c, d, cin, sum, carry, cout); + wire _00_; + wire _01_; + wire _02_; + wire _03_; + wire _04_; + wire _05_; + wire _06_; + wire _07_; + input a; + wire a; + input b; + wire b; + input c; + wire c; + output carry; + wire carry; + input cin; + wire cin; + output cout; + wire cout; + input d; + wire d; + output sum; + wire sum; + sg13g2_nor2_1 _08_ ( + .A(b), + .B(a), + .Y(_07_) + ); + sg13g2_a21oi_2 _09_ ( + .A1(b), + .A2(a), + .B1(c), + .Y(_00_) + ); + sg13g2_nor2_2 _10_ ( + .A(_07_), + .B(_00_), + .Y(cout) + ); + sg13g2_xor2_1 _11_ ( + .A(d), + .B(cin), + .X(_01_) + ); + sg13g2_nand3_1 _12_ ( + .A(b), + .B(a), + .C(c), + .Y(_02_) + ); + sg13g2_nor3_1 _13_ ( + .A(b), + .B(a), + .C(c), + .Y(_03_) + ); + sg13g2_a21o_1 _14_ ( + .A1(cout), + .A2(_02_), + .B1(_03_), + .X(_04_) + ); + sg13g2_xnor2_1 _15_ ( + .A(_01_), + .B(_04_), + .Y(sum) + ); + sg13g2_nand2_1 _16_ ( + .A(d), + .B(cin), + .Y(_05_) + ); + sg13g2_nor2_1 _17_ ( + .A(d), + .B(cin), + .Y(_06_) + ); + sg13g2_a21oi_1 _18_ ( + .A1(_05_), + .A2(_04_), + .B1(_06_), + .Y(carry) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_delay.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_delay.v new file mode 100644 index 00000000..c568cae3 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_delay.v @@ -0,0 +1,26 @@ +// //############################################################################# +// //# Function: Non-inverting Delay Cell # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_delay #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// output z +// ); +// +// assign z = a; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_delay(a, z); + input a; + wire a; + output z; + wire z; + assign z = a; +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffnq.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffnq.v new file mode 100644 index 00000000..f70c8007 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffnq.v @@ -0,0 +1,45 @@ +// //############################################################################# +// //# Function: Negative edge-triggered static D-type flop-flop # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dffnq #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input clk, +// output reg q +// ); +// +// always @(negedge clk) q <= d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dffnq(d, clk, q); + wire _0_; + wire _1_; + wire _2_; + input clk; + wire clk; + input d; + wire d; + output q; + wire q; + sg13g2_inv_2 _3_ ( + .A(clk), + .Y(_0_) + ); + sg13g2_dfrbp_1 _4_ ( + .CLK(_0_), + .D(d), + .Q(q), + .Q_N(_1_), + .RESET_B(_2_) + ); + sg13g2_tiehi _5_ ( + .L_HI(_2_) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffq.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffq.v new file mode 100644 index 00000000..fed94caa --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffq.v @@ -0,0 +1,40 @@ +// //############################################################################# +// //# Function: Positive edge-triggered static D-type flop-flop # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dffq #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input clk, +// output reg q +// ); +// +// always @(posedge clk) q <= d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dffq(d, clk, q); + wire _0_; + wire _1_; + input clk; + wire clk; + input d; + wire d; + output q; + wire q; + sg13g2_dfrbp_1 _2_ ( + .CLK(clk), + .D(d), + .Q(q), + .Q_N(_0_), + .RESET_B(_1_) + ); + sg13g2_tiehi _3_ ( + .L_HI(_1_) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffqn.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffqn.v new file mode 100644 index 00000000..8027ca98 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffqn.v @@ -0,0 +1,45 @@ +// //############################################################################# +// //# Function: Positive edge-triggered inverting static D-type flop-flop # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dffqn #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input clk, +// output reg qn +// ); +// +// always @(posedge clk) qn <= ~d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dffqn(d, clk, qn); + wire _0_; + wire _1_; + wire _2_; + input clk; + wire clk; + input d; + wire d; + output qn; + wire qn; + sg13g2_inv_2 _3_ ( + .A(d), + .Y(_0_) + ); + sg13g2_dfrbp_1 _4_ ( + .CLK(clk), + .D(_0_), + .Q(qn), + .Q_N(_1_), + .RESET_B(_2_) + ); + sg13g2_tiehi _5_ ( + .L_HI(_2_) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffrq.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffrq.v new file mode 100644 index 00000000..282e4e49 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffrq.v @@ -0,0 +1,42 @@ +// //############################################################################# +// //# Function: Positive edge-triggered static D-type flop-flop with async # +// //# active low reset. # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dffrq #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input clk, +// input nreset, +// output reg q +// ); +// +// always @(posedge clk or negedge nreset) +// if (!nreset) q <= 1'b0; +// else q <= d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dffrq(d, clk, nreset, q); + wire _0_; + input clk; + wire clk; + input d; + wire d; + input nreset; + wire nreset; + output q; + wire q; + sg13g2_dfrbp_1 _1_ ( + .CLK(clk), + .D(d), + .Q(q), + .Q_N(_0_), + .RESET_B(nreset) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffrqn.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffrqn.v new file mode 100644 index 00000000..c0cc353a --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffrqn.v @@ -0,0 +1,42 @@ +// //############################################################################# +// //# Function: Positive edge-triggered static inverting D-type flop-flop with # +// // async active low reset. # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dffrqn #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input clk, +// input nreset, +// output reg qn +// ); +// +// always @(posedge clk or negedge nreset) +// if (!nreset) qn <= 1'b1; +// else qn <= ~d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dffrqn(d, clk, nreset, qn); + wire _0_; + input clk; + wire clk; + input d; + wire d; + input nreset; + wire nreset; + output qn; + wire qn; + sg13g2_dfrbp_1 _1_ ( + .CLK(clk), + .D(d), + .Q(_0_), + .Q_N(qn), + .RESET_B(nreset) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffsq.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffsq.v new file mode 100644 index 00000000..3c42cfcc --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffsq.v @@ -0,0 +1,47 @@ +// //############################################################################# +// //# Function: Positive edge-triggered static D-type flop-flop with async # +// //# active low preset. # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dffsq #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input clk, +// input nset, +// output reg q +// ); +// +// always @(posedge clk or negedge nset) +// if (!nset) q <= 1'b1; +// else q <= d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dffsq(d, clk, nset, q); + wire _0_; + wire _1_; + input clk; + wire clk; + input d; + wire d; + input nset; + wire nset; + output q; + wire q; + sg13g2_inv_2 _2_ ( + .A(d), + .Y(_0_) + ); + sg13g2_dfrbp_1 _3_ ( + .CLK(clk), + .D(_0_), + .Q(_1_), + .Q_N(q), + .RESET_B(nset) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffsqn.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffsqn.v new file mode 100644 index 00000000..23601a93 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dffsqn.v @@ -0,0 +1,47 @@ +// //############################################################################# +// //# Function: Positive edge-triggered static inverting D-type flop-flop with # +// // async active low set. # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dffsqn #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input clk, +// input nset, +// output reg qn +// ); +// +// always @(posedge clk or negedge nset) +// if (!nset) qn <= 1'b0; +// else qn <= ~d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dffsqn(d, clk, nset, qn); + wire _0_; + wire _1_; + input clk; + wire clk; + input d; + wire d; + input nset; + wire nset; + output qn; + wire qn; + sg13g2_inv_2 _2_ ( + .A(d), + .Y(_0_) + ); + sg13g2_dfrbp_1 _3_ ( + .CLK(clk), + .D(_0_), + .Q(qn), + .Q_N(_1_), + .RESET_B(nset) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux2.v new file mode 100644 index 00000000..c9957a3d --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux2.v @@ -0,0 +1,46 @@ +// //############################################################################# +// //# Function: 2-Input one-hot mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dmux2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input sel1, +// input sel0, +// input in1, +// input in0, +// output out +// ); +// +// assign out = (sel0 & in0) | (sel1 & in1); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dmux2(sel1, sel0, in1, in0, out); + wire _0_; + input in0; + wire in0; + input in1; + wire in1; + output out; + wire out; + input sel0; + wire sel0; + input sel1; + wire sel1; + sg13g2_a22oi_1 _1_ ( + .A1(in0), + .A2(sel0), + .B1(in1), + .B2(sel1), + .Y(_0_) + ); + sg13g2_inv_1 _2_ ( + .A(_0_), + .Y(out) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux3.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux3.v new file mode 100644 index 00000000..d04f53c4 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux3.v @@ -0,0 +1,59 @@ +// //############################################################################# +// //# Function: 3-Input one-hot mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dmux3 #( +// parameter PROP = "DEFAULT" +// ) ( +// input sel0, +// input sel1, +// input sel2, +// input in0, +// input in1, +// input in2, +// output out +// ); +// +// assign out = (sel0 & in0) | (sel1 & in1) | (sel2 & in2); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dmux3(sel0, sel1, sel2, in0, in1, in2, out); + wire _0_; + wire _1_; + input in0; + wire in0; + input in1; + wire in1; + input in2; + wire in2; + output out; + wire out; + input sel0; + wire sel0; + input sel1; + wire sel1; + input sel2; + wire sel2; + sg13g2_nand2_1 _2_ ( + .A(in1), + .B(sel1), + .Y(_0_) + ); + sg13g2_a22oi_1 _3_ ( + .A1(in2), + .A2(sel2), + .B1(in0), + .B2(sel0), + .Y(_1_) + ); + sg13g2_nand2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(out) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux4.v new file mode 100644 index 00000000..cbfe4fd4 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux4.v @@ -0,0 +1,67 @@ +// //############################################################################# +// //# Function: 4-Input one-hot mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dmux4 #( +// parameter PROP = "DEFAULT" // cell property +// ) ( +// input sel3, +// input sel2, +// input sel1, +// input sel0, +// input in3, +// input in2, +// input in1, +// input in0, +// output out +// ); +// +// assign out = (sel0 & in0) | (sel1 & in1) | (sel2 & in2) | (sel3 & in3); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dmux4(sel3, sel2, sel1, sel0, in3, in2, in1, in0, out); + wire _0_; + wire _1_; + input in0; + wire in0; + input in1; + wire in1; + input in2; + wire in2; + input in3; + wire in3; + output out; + wire out; + input sel0; + wire sel0; + input sel1; + wire sel1; + input sel2; + wire sel2; + input sel3; + wire sel3; + sg13g2_a22oi_1 _2_ ( + .A1(in0), + .A2(sel0), + .B1(in2), + .B2(sel2), + .Y(_0_) + ); + sg13g2_a22oi_1 _3_ ( + .A1(in1), + .A2(sel1), + .B1(in3), + .B2(sel3), + .Y(_1_) + ); + sg13g2_nand2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(out) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux5.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux5.v new file mode 100644 index 00000000..5f8d3742 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux5.v @@ -0,0 +1,80 @@ +// //############################################################################# +// //# Function: 5-Input one-hot mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dmux5 #( +// parameter PROP = "DEFAULT" // cell property +// ) ( +// input sel4, +// input sel3, +// input sel2, +// input sel1, +// input sel0, +// input in4, +// input in3, +// input in2, +// input in1, +// input in0, +// output out +// ); +// +// assign out = (sel0 & in0) | (sel1 & in1) | (sel2 & in2) | (sel3 & in3) | (sel4 & in4); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dmux5(sel4, sel3, sel2, sel1, sel0, in4, in3, in2, in1, in0, out); + wire _0_; + wire _1_; + wire _2_; + input in0; + wire in0; + input in1; + wire in1; + input in2; + wire in2; + input in3; + wire in3; + input in4; + wire in4; + output out; + wire out; + input sel0; + wire sel0; + input sel1; + wire sel1; + input sel2; + wire sel2; + input sel3; + wire sel3; + input sel4; + wire sel4; + sg13g2_nand2_1 _3_ ( + .A(in1), + .B(sel1), + .Y(_0_) + ); + sg13g2_a22oi_1 _4_ ( + .A1(in0), + .A2(sel0), + .B1(in4), + .B2(sel4), + .Y(_1_) + ); + sg13g2_a22oi_1 _5_ ( + .A1(in2), + .A2(sel2), + .B1(in3), + .B2(sel3), + .Y(_2_) + ); + sg13g2_nand3_1 _6_ ( + .A(_0_), + .B(_1_), + .C(_2_), + .Y(out) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux6.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux6.v new file mode 100644 index 00000000..ff229220 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux6.v @@ -0,0 +1,93 @@ +// //############################################################################# +// //# Function: 6-Input one-hot mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dmux6 #( +// parameter PROP = "DEFAULT" // cell property +// ) ( +// input sel5, +// input sel4, +// input sel3, +// input sel2, +// input sel1, +// input sel0, +// input in5, +// input in4, +// input in3, +// input in2, +// input in1, +// input in0, +// output out +// ); +// +// assign out = (sel0 & in0) | +// (sel1 & in1) | +// (sel2 & in2) | +// (sel3 & in3) | +// (sel4 & in4) | +// (sel5 & in5); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dmux6(sel5, sel4, sel3, sel2, sel1, sel0, in5, in4, in3, in2, in1, in0, out); + wire _0_; + wire _1_; + wire _2_; + input in0; + wire in0; + input in1; + wire in1; + input in2; + wire in2; + input in3; + wire in3; + input in4; + wire in4; + input in5; + wire in5; + output out; + wire out; + input sel0; + wire sel0; + input sel1; + wire sel1; + input sel2; + wire sel2; + input sel3; + wire sel3; + input sel4; + wire sel4; + input sel5; + wire sel5; + sg13g2_a22oi_1 _3_ ( + .A1(in1), + .A2(sel1), + .B1(in4), + .B2(sel4), + .Y(_0_) + ); + sg13g2_a22oi_1 _4_ ( + .A1(in3), + .A2(sel3), + .B1(in5), + .B2(sel5), + .Y(_1_) + ); + sg13g2_a22oi_1 _5_ ( + .A1(in0), + .A2(sel0), + .B1(in2), + .B2(sel2), + .Y(_2_) + ); + sg13g2_nand3_1 _6_ ( + .A(_0_), + .B(_1_), + .C(_2_), + .Y(out) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux7.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux7.v new file mode 100644 index 00000000..b7b7e112 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux7.v @@ -0,0 +1,107 @@ +// //############################################################################# +// //# Function: 7-Input one-hot mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dmux7 #( +// parameter PROP = "DEFAULT" // cell property +// ) ( +// input sel6, +// input sel5, +// input sel4, +// input sel3, +// input sel2, +// input sel1, +// input sel0, +// input in6, +// input in5, +// input in4, +// input in3, +// input in2, +// input in1, +// input in0, +// output out +// ); +// +// assign out = (sel0 & in0) | +// (sel1 & in1) | +// (sel2 & in2) | +// (sel3 & in3) | +// (sel4 & in4) | +// (sel5 & in5) | +// (sel6 & in6); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dmux7(sel6, sel5, sel4, sel3, sel2, sel1, sel0, in6, in5, in4, in3, in2, in1, in0, out); + wire _0_; + wire _1_; + wire _2_; + wire _3_; + input in0; + wire in0; + input in1; + wire in1; + input in2; + wire in2; + input in3; + wire in3; + input in4; + wire in4; + input in5; + wire in5; + input in6; + wire in6; + output out; + wire out; + input sel0; + wire sel0; + input sel1; + wire sel1; + input sel2; + wire sel2; + input sel3; + wire sel3; + input sel4; + wire sel4; + input sel5; + wire sel5; + input sel6; + wire sel6; + sg13g2_nand2_1 _4_ ( + .A(in2), + .B(sel2), + .Y(_0_) + ); + sg13g2_a22oi_1 _5_ ( + .A1(in0), + .A2(sel0), + .B1(in3), + .B2(sel3), + .Y(_1_) + ); + sg13g2_a22oi_1 _6_ ( + .A1(in1), + .A2(sel1), + .B1(in4), + .B2(sel4), + .Y(_2_) + ); + sg13g2_a22oi_1 _7_ ( + .A1(in5), + .A2(sel5), + .B1(in6), + .B2(sel6), + .Y(_3_) + ); + sg13g2_nand4_1 _8_ ( + .A(_0_), + .B(_1_), + .C(_2_), + .D(_3_), + .Y(out) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux8.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux8.v new file mode 100644 index 00000000..0c835d04 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_dmux8.v @@ -0,0 +1,121 @@ +// //############################################################################# +// //# Function: 8-Input one hot mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_dmux8 #( +// parameter PROP = "DEFAULT" // cell property +// ) ( +// input sel7, +// input sel6, +// input sel5, +// input sel4, +// input sel3, +// input sel2, +// input sel1, +// input sel0, +// input in7, +// input in6, +// input in5, +// input in4, +// input in3, +// input in2, +// input in1, +// input in0, +// output out +// ); +// +// assign out = (sel0 & in0) | +// (sel1 & in1) | +// (sel2 & in2) | +// (sel3 & in3) | +// (sel4 & in4) | +// (sel5 & in5) | +// (sel6 & in6) | +// (sel7 & in7); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_dmux8(sel7, sel6, sel5, sel4, sel3, sel2, sel1, sel0, in7, in6, in5, in4, in3, in2, in1, in0, out); + wire _00_; + wire _01_; + wire _02_; + wire _03_; + wire _04_; + input in0; + wire in0; + input in1; + wire in1; + input in2; + wire in2; + input in3; + wire in3; + input in4; + wire in4; + input in5; + wire in5; + input in6; + wire in6; + input in7; + wire in7; + output out; + wire out; + input sel0; + wire sel0; + input sel1; + wire sel1; + input sel2; + wire sel2; + input sel3; + wire sel3; + input sel4; + wire sel4; + input sel5; + wire sel5; + input sel6; + wire sel6; + input sel7; + wire sel7; + sg13g2_a22oi_1 _05_ ( + .A1(in3), + .A2(sel3), + .B1(in6), + .B2(sel6), + .Y(_00_) + ); + sg13g2_a22oi_1 _06_ ( + .A1(in0), + .A2(sel0), + .B1(in7), + .B2(sel7), + .Y(_01_) + ); + sg13g2_and2_1 _07_ ( + .A(_00_), + .B(_01_), + .X(_02_) + ); + sg13g2_a22oi_1 _08_ ( + .A1(in2), + .A2(sel2), + .B1(in5), + .B2(sel5), + .Y(_03_) + ); + sg13g2_a22oi_1 _09_ ( + .A1(in1), + .A2(sel1), + .B1(in4), + .B2(sel4), + .Y(_04_) + ); + sg13g2_nand3_1 _10_ ( + .A(_02_), + .B(_03_), + .C(_04_), + .Y(out) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_inv.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_inv.v new file mode 100644 index 00000000..65419651 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_inv.v @@ -0,0 +1,29 @@ +// //############################################################################# +// //# Function: Inverter # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_inv #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// output z +// ); +// +// assign z = ~a; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_inv(a, z); + input a; + wire a; + output z; + wire z; + sg13g2_inv_2 _0_ ( + .A(a), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_latnq.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_latnq.v new file mode 100644 index 00000000..1d97a217 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_latnq.v @@ -0,0 +1,38 @@ +// //############################################################################# +// //# Function: D-type active-low transparent latch # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_latnq #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input clk, +// output reg q +// ); +// +// always @(clk or d) if (~clk) q <= d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_latnq(d, clk, q); + wire _0_; + input clk; + wire clk; + input d; + wire d; + output q; + wire q; + sg13g2_inv_2 _1_ ( + .A(clk), + .Y(_0_) + ); + sg13g2_dlhq_1 _2_ ( + .D(d), + .GATE(_0_), + .Q(q) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_latq.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_latq.v new file mode 100644 index 00000000..d19daa66 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_latq.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: D-type active-high transparent latch # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_latq #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input clk, +// output reg q +// ); +// +// always @(clk or d) if (clk) q <= d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_latq(d, clk, q); + input clk; + wire clk; + input d; + wire d; + output q; + wire q; + sg13g2_dlhq_1 _0_ ( + .D(d), + .GATE(clk), + .Q(q) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_mux2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_mux2.v new file mode 100644 index 00000000..a4fdaf31 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_mux2.v @@ -0,0 +1,37 @@ +// //############################################################################# +// //# Function: 2-Input Mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_mux2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input d0, +// input d1, +// input s, +// output z +// ); +// +// assign z = (d0 & ~s) | (d1 & s); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_mux2(d0, d1, s, z); + input d0; + wire d0; + input d1; + wire d1; + input s; + wire s; + output z; + wire z; + sg13g2_mux2_1 _0_ ( + .A0(d0), + .A1(d1), + .S(s), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_mux3.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_mux3.v new file mode 100644 index 00000000..d3b4e44c --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_mux3.v @@ -0,0 +1,50 @@ +// //############################################################################# +// //# Function: 3-Input Mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_mux3 #( +// parameter PROP = "DEFAULT" +// ) ( +// input d0, +// input d1, +// input d2, +// input s0, +// input s1, +// output z +// ); +// +// assign z = (d0 & ~s0 & ~s1) | (d1 & s0 & ~s1) | (d2 & s1); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_mux3(d0, d1, d2, s0, s1, z); + wire _0_; + input d0; + wire d0; + input d1; + wire d1; + input d2; + wire d2; + input s0; + wire s0; + input s1; + wire s1; + output z; + wire z; + sg13g2_mux2_1 _1_ ( + .A0(d0), + .A1(d1), + .S(s0), + .X(_0_) + ); + sg13g2_mux2_1 _2_ ( + .A0(_0_), + .A1(d2), + .S(s1), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_mux4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_mux4.v new file mode 100644 index 00000000..0f5c39d3 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_mux4.v @@ -0,0 +1,49 @@ +// //############################################################################# +// //# Function: 4-Input Mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_mux4 #( +// parameter PROP = "DEFAULT" +// ) ( +// input d0, +// input d1, +// input d2, +// input d3, +// input s0, +// input s1, +// output z +// ); +// +// assign z = (d0 & ~s1 & ~s0) | (d1 & ~s1 & s0) | (d2 & s1 & ~s0) | (d3 & s1 & s0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_mux4(d0, d1, d2, d3, s0, s1, z); + input d0; + wire d0; + input d1; + wire d1; + input d2; + wire d2; + input d3; + wire d3; + input s0; + wire s0; + input s1; + wire s1; + output z; + wire z; + sg13g2_mux4_1 _0_ ( + .A0(d0), + .A1(d1), + .A2(d2), + .A3(d3), + .S0(s0), + .S1(s1), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_muxi2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_muxi2.v new file mode 100644 index 00000000..1bcb322a --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_muxi2.v @@ -0,0 +1,43 @@ +// //############################################################################# +// //# Function: 2-Input Inverting Mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_muxi2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input d0, +// input d1, +// input s, +// output z +// ); +// +// assign z = ~((d0 & ~s) | (d1 & s)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_muxi2(d0, d1, s, z); + wire _0_; + input d0; + wire d0; + input d1; + wire d1; + input s; + wire s; + output z; + wire z; + sg13g2_nand2b_1 _1_ ( + .A_N(d1), + .B(s), + .Y(_0_) + ); + sg13g2_o21ai_1 _2_ ( + .A1(d0), + .A2(s), + .B1(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_muxi3.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_muxi3.v new file mode 100644 index 00000000..0fdf504a --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_muxi3.v @@ -0,0 +1,56 @@ +// //############################################################################# +// //# Function: 3-Input Inverting Mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_muxi3 #( +// parameter PROP = "DEFAULT" +// ) ( +// input d0, +// input d1, +// input d2, +// input s0, +// input s1, +// output z +// ); +// +// assign z = ~((d0 & ~s0 & ~s1) | (d1 & s0 & ~s1) | (d2 & s1)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_muxi3(d0, d1, d2, s0, s1, z); + wire _0_; + wire _1_; + input d0; + wire d0; + input d1; + wire d1; + input d2; + wire d2; + input s0; + wire s0; + input s1; + wire s1; + output z; + wire z; + sg13g2_mux2_1 _2_ ( + .A0(d0), + .A1(d1), + .S(s0), + .X(_0_) + ); + sg13g2_nand2b_1 _3_ ( + .A_N(d2), + .B(s1), + .Y(_1_) + ); + sg13g2_o21ai_1 _4_ ( + .A1(s1), + .A2(_0_), + .B1(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_muxi4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_muxi4.v new file mode 100644 index 00000000..83b45534 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_muxi4.v @@ -0,0 +1,54 @@ +// //############################################################################# +// //# Function: 4-Input Inverting Mux # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_muxi4 #( +// parameter PROP = "DEFAULT" +// ) ( +// input d0, +// input d1, +// input d2, +// input d3, +// input s0, +// input s1, +// output z +// ); +// +// assign z = ~((d0 & ~s1 & ~s0) | (d1 & ~s1 & s0) | (d2 & s1 & ~s0) | (d3 & s1 & s0)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_muxi4(d0, d1, d2, d3, s0, s1, z); + wire _0_; + input d0; + wire d0; + input d1; + wire d1; + input d2; + wire d2; + input d3; + wire d3; + input s0; + wire s0; + input s1; + wire s1; + output z; + wire z; + sg13g2_mux4_1 _1_ ( + .A0(d0), + .A1(d1), + .A2(d2), + .A3(d3), + .S0(s0), + .S1(s1), + .X(_0_) + ); + sg13g2_inv_1 _2_ ( + .A(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nand2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nand2.v new file mode 100644 index 00000000..d4b785d6 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nand2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2 Input Nand Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_nand2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = ~(a & b); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_nand2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_nand2_2 _0_ ( + .A(b), + .B(a), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nand3.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nand3.v new file mode 100644 index 00000000..a769556f --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nand3.v @@ -0,0 +1,37 @@ +// //############################################################################# +// //# Function: 3 Input Nand Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_nand3 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// output z +// ); +// +// assign z = ~(a & b & c); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_nand3(a, b, c, z); + input a; + wire a; + input b; + wire b; + input c; + wire c; + output z; + wire z; + sg13g2_nand3_1 _0_ ( + .A(b), + .B(a), + .C(c), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nand4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nand4.v new file mode 100644 index 00000000..6d516430 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nand4.v @@ -0,0 +1,41 @@ +// //############################################################################# +// //# Function: 4 Input Nand Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_nand4 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// input d, +// output z +// ); +// +// assign z = ~(a & b & c & d); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_nand4(a, b, c, d, z); + input a; + wire a; + input b; + wire b; + input c; + wire c; + input d; + wire d; + output z; + wire z; + sg13g2_nand4_1 _0_ ( + .A(b), + .B(a), + .C(c), + .D(d), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nor2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nor2.v new file mode 100644 index 00000000..d579f3ae --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nor2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2 Input Nor Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_nor2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = ~(a | b); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_nor2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_nor2_2 _0_ ( + .A(b), + .B(a), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nor3.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nor3.v new file mode 100644 index 00000000..cb48b29a --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nor3.v @@ -0,0 +1,37 @@ +// //############################################################################# +// //# Function: 3 Input Nor Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_nor3 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// output z +// ); +// +// assign z = ~(a | b | c); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_nor3(a, b, c, z); + input a; + wire a; + input b; + wire b; + input c; + wire c; + output z; + wire z; + sg13g2_nor3_2 _0_ ( + .A(b), + .B(a), + .C(c), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nor4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nor4.v new file mode 100644 index 00000000..bae3402a --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_nor4.v @@ -0,0 +1,41 @@ +// //############################################################################# +// //# Function: 4 Input Nor Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_nor4 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// input d, +// output z +// ); +// +// assign z = ~(a | b | c | d); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_nor4(a, b, c, d, z); + input a; + wire a; + input b; + wire b; + input c; + wire c; + input d; + wire d; + output z; + wire z; + sg13g2_nor4_2 _0_ ( + .A(b), + .B(a), + .C(c), + .D(d), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa21.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa21.v new file mode 100644 index 00000000..1f120769 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa21.v @@ -0,0 +1,42 @@ +// //############################################################################# +// //# Function: Or-And (oa21) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oa21 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// output z +// ); +// +// assign z = (a0 | a1) & b0; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oa21(a0, a1, b0, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + output z; + wire z; + sg13g2_o21ai_1 _1_ ( + .A1(a1), + .A2(a0), + .B1(b0), + .Y(_0_) + ); + sg13g2_inv_1 _2_ ( + .A(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa211.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa211.v new file mode 100644 index 00000000..09c9603a --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa211.v @@ -0,0 +1,51 @@ +// //############################################################################# +// //# Function: Or-And (oa211) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oa211 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input c0, +// output z +// ); +// +// assign z = (a0 | a1) & b0 & c0; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oa211(a0, a1, b0, c0, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input c0; + wire c0; + output z; + wire z; + sg13g2_inv_1 _2_ ( + .A(c0), + .Y(_0_) + ); + sg13g2_o21ai_1 _3_ ( + .A1(a1), + .A2(a0), + .B1(b0), + .Y(_1_) + ); + sg13g2_nor2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa22.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa22.v new file mode 100644 index 00000000..410bb09e --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa22.v @@ -0,0 +1,51 @@ +// //############################################################################# +// //# Function: Or-And (oa22) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oa22 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// output z +// ); +// +// assign z = (a0 | a1) & (b0 | b1); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oa22(a0, a1, b0, b1, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + output z; + wire z; + sg13g2_nor2_2 _2_ ( + .A(a1), + .B(a0), + .Y(_0_) + ); + sg13g2_nor2_2 _3_ ( + .A(b1), + .B(b0), + .Y(_1_) + ); + sg13g2_nor2_2 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa221.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa221.v new file mode 100644 index 00000000..da6b918e --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa221.v @@ -0,0 +1,55 @@ +// //############################################################################# +// //# Function: Or-And (oa221) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oa221 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// input c0, +// output z +// ); +// +// assign z = (a0 | a1) & (b0 | b1) & (c0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oa221(a0, a1, b0, b1, c0, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + input c0; + wire c0; + output z; + wire z; + sg13g2_nor2_1 _2_ ( + .A(a1), + .B(a0), + .Y(_0_) + ); + sg13g2_o21ai_1 _3_ ( + .A1(b1), + .A2(b0), + .B1(c0), + .Y(_1_) + ); + sg13g2_nor2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa222.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa222.v new file mode 100644 index 00000000..fec622d7 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa222.v @@ -0,0 +1,64 @@ +// //############################################################################# +// //# Function: Or-And (oa222) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oa222 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// input c0, +// input c1, +// output z +// ); +// +// assign z = (a0 | a1) & (b0 | b1) & (c0 | c1); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oa222(a0, a1, b0, b1, c0, c1, z); + wire _0_; + wire _1_; + wire _2_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + input c0; + wire c0; + input c1; + wire c1; + output z; + wire z; + sg13g2_nor2_2 _3_ ( + .A(b1), + .B(b0), + .Y(_1_) + ); + sg13g2_nor2_2 _4_ ( + .A(a1), + .B(a0), + .Y(_2_) + ); + sg13g2_nor2_1 _5_ ( + .A(c1), + .B(c0), + .Y(_0_) + ); + sg13g2_nor3_2 _6_ ( + .A(_1_), + .B(_2_), + .C(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa31.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa31.v new file mode 100644 index 00000000..7e544687 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa31.v @@ -0,0 +1,46 @@ +// //############################################################################# +// //# Function: Or-And (oa31) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oa31 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// output z +// ); +// +// assign z = (a0 | a1 | a2) & b0; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oa31(a0, a1, a2, b0, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + output z; + wire z; + sg13g2_nor3_2 _1_ ( + .A(a1), + .B(a0), + .C(a2), + .Y(_0_) + ); + sg13g2_nor2b_1 _2_ ( + .A(_0_), + .B_N(b0), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa311.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa311.v new file mode 100644 index 00000000..be8ed073 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa311.v @@ -0,0 +1,55 @@ +// //############################################################################# +// //# Function: Or-And (oa311) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oa311 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input c0, +// output z +// ); +// +// assign z = (a0 | a1 | a2) & b0 & c0; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oa311(a0, a1, a2, b0, c0, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input c0; + wire c0; + output z; + wire z; + sg13g2_nor3_2 _2_ ( + .A(a1), + .B(a0), + .C(a2), + .Y(_0_) + ); + sg13g2_nand2_1 _3_ ( + .A(b0), + .B(c0), + .Y(_1_) + ); + sg13g2_nor2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa32.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa32.v new file mode 100644 index 00000000..aca7762e --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa32.v @@ -0,0 +1,55 @@ +// //############################################################################# +// //# Function: Or-And (oa32) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oa32 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input b1, +// output z +// ); +// +// assign z = (a0 | a1 | a2) & (b0 | b1); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oa32(a0, a1, a2, b0, b1, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input b1; + wire b1; + output z; + wire z; + sg13g2_nor2_1 _2_ ( + .A(b1), + .B(b0), + .Y(_0_) + ); + sg13g2_nor3_2 _3_ ( + .A(a1), + .B(a0), + .C(a2), + .Y(_1_) + ); + sg13g2_nor2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa33.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa33.v new file mode 100644 index 00000000..f67a2ca7 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oa33.v @@ -0,0 +1,59 @@ +// //############################################################################# +// //# Function: Or-And (oa33) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oa33 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input b1, +// input b2, +// output z +// ); +// +// assign z = (a0 | a1 | a2) & (b0 | b1 | b2); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oa33(a0, a1, a2, b0, b1, b2, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input b1; + wire b1; + input b2; + wire b2; + output z; + wire z; + sg13g2_nor3_2 _2_ ( + .A(a1), + .B(a0), + .C(a2), + .Y(_0_) + ); + sg13g2_nor3_2 _3_ ( + .A(b2), + .B(b1), + .C(b0), + .Y(_1_) + ); + sg13g2_nor2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai21.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai21.v new file mode 100644 index 00000000..4d321926 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai21.v @@ -0,0 +1,37 @@ +// //############################################################################# +// //# Function: Or-And-Inverter (oai21) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oai21 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// output z +// ); +// +// assign z = ~((a0 | a1) & b0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oai21(a0, a1, b0, z); + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + output z; + wire z; + sg13g2_o21ai_1 _0_ ( + .A1(a1), + .A2(a0), + .B1(b0), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai22.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai22.v new file mode 100644 index 00000000..f155c509 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai22.v @@ -0,0 +1,46 @@ +// //############################################################################# +// //# Function: Or-And-Inverter (oai22) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oai22 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// output z +// ); +// +// assign z = ~((a0 | a1) & (b0 | b1)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oai22(a0, a1, b0, b1, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + output z; + wire z; + sg13g2_or2_1 _1_ ( + .A(b1), + .B(b0), + .X(_0_) + ); + sg13g2_o21ai_1 _2_ ( + .A1(a1), + .A2(a0), + .B1(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai221.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai221.v new file mode 100644 index 00000000..d7951fbc --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai221.v @@ -0,0 +1,55 @@ +// //############################################################################# +// //# Function: Or-And-Inverter (oai221) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oai221 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// input c0, +// output z +// ); +// +// assign z = ~((a0 | a1) & (b0 | b1) & (c0)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oai221(a0, a1, b0, b1, c0, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + input c0; + wire c0; + output z; + wire z; + sg13g2_nor2_1 _2_ ( + .A(a1), + .B(a0), + .Y(_0_) + ); + sg13g2_o21ai_1 _3_ ( + .A1(b1), + .A2(b0), + .B1(c0), + .Y(_1_) + ); + sg13g2_or2_1 _4_ ( + .A(_0_), + .B(_1_), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai222.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai222.v new file mode 100644 index 00000000..3b0125c2 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai222.v @@ -0,0 +1,64 @@ +// //############################################################################# +// //# Function: Or-And-Inverter (oai222) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oai222 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input b0, +// input b1, +// input c0, +// input c1, +// output z +// ); +// +// assign z = ~((a0 | a1) & (b0 | b1) & (c0 | c1)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oai222(a0, a1, b0, b1, c0, c1, z); + wire _0_; + wire _1_; + wire _2_; + input a0; + wire a0; + input a1; + wire a1; + input b0; + wire b0; + input b1; + wire b1; + input c0; + wire c0; + input c1; + wire c1; + output z; + wire z; + sg13g2_nor2_2 _3_ ( + .A(b1), + .B(b0), + .Y(_1_) + ); + sg13g2_nor2_1 _4_ ( + .A(c1), + .B(c0), + .Y(_2_) + ); + sg13g2_nor2_1 _5_ ( + .A(a1), + .B(a0), + .Y(_0_) + ); + sg13g2_or3_1 _6_ ( + .A(_1_), + .B(_2_), + .C(_0_), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai31.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai31.v new file mode 100644 index 00000000..a898a275 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai31.v @@ -0,0 +1,46 @@ +// //############################################################################# +// //# Function: Or-And-Inverter (oai31) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oai31 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// output z +// ); +// +// assign z = ~((a0 | a1 | a2) & b0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oai31(a0, a1, a2, b0, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + output z; + wire z; + sg13g2_nor3_2 _1_ ( + .A(a1), + .B(a0), + .C(a2), + .Y(_0_) + ); + sg13g2_nand2b_1 _2_ ( + .A_N(_0_), + .B(b0), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai311.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai311.v new file mode 100644 index 00000000..a299f552 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai311.v @@ -0,0 +1,50 @@ +// //############################################################################# +// //# Function: Or-And-Inverter (oai311) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oai311 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input c0, +// output z +// ); +// +// assign z = ~((a0 | a1 | a2) & b0 & c0); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oai311(a0, a1, a2, b0, c0, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input c0; + wire c0; + output z; + wire z; + sg13g2_or3_1 _1_ ( + .A(a1), + .B(a0), + .C(a2), + .X(_0_) + ); + sg13g2_nand3_1 _2_ ( + .A(c0), + .B(b0), + .C(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai32.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai32.v new file mode 100644 index 00000000..54b85c69 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai32.v @@ -0,0 +1,50 @@ +// //############################################################################# +// //# Function: Or-And-Inverter (oai32) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oai32 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input b1, +// output z +// ); +// +// assign z = ~((a0 | a1 | a2) & (b0 | b1)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oai32(a0, a1, a2, b0, b1, z); + wire _0_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input b1; + wire b1; + output z; + wire z; + sg13g2_or3_1 _1_ ( + .A(a1), + .B(a0), + .C(a2), + .X(_0_) + ); + sg13g2_o21ai_1 _2_ ( + .A1(b1), + .A2(b0), + .B1(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai33.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai33.v new file mode 100644 index 00000000..917f2934 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_oai33.v @@ -0,0 +1,59 @@ +// //############################################################################# +// //# Function: Or-And-Inverter (oai33) Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_oai33 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a0, +// input a1, +// input a2, +// input b0, +// input b1, +// input b2, +// output z +// ); +// +// assign z = ~((a0 | a1 | a2) & (b0 | b1 | b2)); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_oai33(a0, a1, a2, b0, b1, b2, z); + wire _0_; + wire _1_; + input a0; + wire a0; + input a1; + wire a1; + input a2; + wire a2; + input b0; + wire b0; + input b1; + wire b1; + input b2; + wire b2; + output z; + wire z; + sg13g2_nor3_2 _2_ ( + .A(b1), + .B(b0), + .C(b2), + .Y(_0_) + ); + sg13g2_nor3_2 _3_ ( + .A(a2), + .B(a1), + .C(a0), + .Y(_1_) + ); + sg13g2_or2_1 _4_ ( + .A(_0_), + .B(_1_), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_or2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_or2.v new file mode 100644 index 00000000..25e64aec --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_or2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2 Input Or Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_or2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = a | b; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_or2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_or2_1 _0_ ( + .A(b), + .B(a), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_or3.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_or3.v new file mode 100644 index 00000000..964950a6 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_or3.v @@ -0,0 +1,37 @@ +// //############################################################################# +// //# Function: 3 Input Or Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_or3 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// output z +// ); +// +// assign z = a | b | c; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_or3(a, b, c, z); + input a; + wire a; + input b; + wire b; + input c; + wire c; + output z; + wire z; + sg13g2_or3_1 _0_ ( + .A(b), + .B(a), + .C(c), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_or4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_or4.v new file mode 100644 index 00000000..52e46e2f --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_or4.v @@ -0,0 +1,41 @@ +// //############################################################################# +// //# Function: 4 Input Or Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_or4 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// input d, +// output z +// ); +// +// assign z = a | b | c | d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_or4(a, b, c, d, z); + input a; + wire a; + input b; + wire b; + input c; + wire c; + input d; + wire d; + output z; + wire z; + sg13g2_or4_1 _0_ ( + .A(b), + .B(a), + .C(c), + .D(d), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffq.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffq.v new file mode 100644 index 00000000..fca14d1e --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffq.v @@ -0,0 +1,54 @@ +// //############################################################################# +// //# Function: Positive edge-triggered static D-type flop-flop with scan input # +// //# # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_sdffq #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input si, +// input se, +// input clk, +// output reg q +// ); +// +// always @(posedge clk) q <= se ? si : d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_sdffq(d, si, se, clk, q); + wire _0_; + wire _1_; + wire _2_; + input clk; + wire clk; + input d; + wire d; + output q; + wire q; + input se; + wire se; + input si; + wire si; + sg13g2_mux2_1 _3_ ( + .A0(d), + .A1(si), + .S(se), + .X(_0_) + ); + sg13g2_dfrbp_1 _4_ ( + .CLK(clk), + .D(_0_), + .Q(q), + .Q_N(_1_), + .RESET_B(_2_) + ); + sg13g2_tiehi _5_ ( + .L_HI(_2_) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffqn.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffqn.v new file mode 100644 index 00000000..088cb627 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffqn.v @@ -0,0 +1,60 @@ +// //############################################################################# +// //# Function: Positive edge-triggered inverting static D-type flop-flop # +// //# with scan input. # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_sdffqn #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input si, +// input se, +// input clk, +// output reg qn +// ); +// +// always @(posedge clk) qn <= se ? ~si : ~d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_sdffqn(d, si, se, clk, qn); + wire _0_; + wire _1_; + wire _2_; + wire _3_; + input clk; + wire clk; + input d; + wire d; + output qn; + wire qn; + input se; + wire se; + input si; + wire si; + sg13g2_nand2b_1 _4_ ( + .A_N(si), + .B(se), + .Y(_1_) + ); + sg13g2_o21ai_1 _5_ ( + .A1(d), + .A2(se), + .B1(_1_), + .Y(_0_) + ); + sg13g2_dfrbp_1 _6_ ( + .CLK(clk), + .D(_0_), + .Q(qn), + .Q_N(_2_), + .RESET_B(_3_) + ); + sg13g2_tiehi _7_ ( + .L_HI(_3_) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffrq.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffrq.v new file mode 100644 index 00000000..d33adb3c --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffrq.v @@ -0,0 +1,55 @@ +// //############################################################################# +// //# Function: Positive edge-triggered static D-type flop-flop with async # +// //# active low reset and scan input # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_sdffrq #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input si, +// input se, +// input clk, +// input nreset, +// output reg q +// ); +// +// always @(posedge clk or negedge nreset) +// if (!nreset) q <= 1'b0; +// else q <= se ? si : d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_sdffrq(d, si, se, clk, nreset, q); + wire _0_; + wire _1_; + input clk; + wire clk; + input d; + wire d; + input nreset; + wire nreset; + output q; + wire q; + input se; + wire se; + input si; + wire si; + sg13g2_mux2_1 _2_ ( + .A0(d), + .A1(si), + .S(se), + .X(_0_) + ); + sg13g2_dfrbp_1 _3_ ( + .CLK(clk), + .D(_0_), + .Q(q), + .Q_N(_1_), + .RESET_B(nreset) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffrqn.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffrqn.v new file mode 100644 index 00000000..36a7b54e --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffrqn.v @@ -0,0 +1,55 @@ +// //############################################################################# +// //# Function: Positive edge-triggered static inverting D-type flop-flop with # +// // async active low reset and scan input # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_sdffrqn #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input si, +// input se, +// input clk, +// input nreset, +// output reg qn +// ); +// +// always @(posedge clk or negedge nreset) +// if (!nreset) qn <= 1'b1; +// else qn <= se ? ~si : ~d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_sdffrqn(d, si, se, clk, nreset, qn); + wire _0_; + wire _1_; + input clk; + wire clk; + input d; + wire d; + input nreset; + wire nreset; + output qn; + wire qn; + input se; + wire se; + input si; + wire si; + sg13g2_mux2_1 _2_ ( + .A0(d), + .A1(si), + .S(se), + .X(_0_) + ); + sg13g2_dfrbp_1 _3_ ( + .CLK(clk), + .D(_0_), + .Q(_1_), + .Q_N(qn), + .RESET_B(nreset) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffsq.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffsq.v new file mode 100644 index 00000000..1dc7e6eb --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffsq.v @@ -0,0 +1,61 @@ +// //############################################################################# +// //# Function: Positive edge-triggered static D-type flop-flop with async # +// //# active low preset and scan input. # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_sdffsq #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input si, +// input se, +// input clk, +// input nset, +// output reg q +// ); +// +// always @(posedge clk or negedge nset) +// if (!nset) q <= 1'b1; +// else q <= se ? si : d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_sdffsq(d, si, se, clk, nset, q); + wire _0_; + wire _1_; + wire _2_; + input clk; + wire clk; + input d; + wire d; + input nset; + wire nset; + output q; + wire q; + input se; + wire se; + input si; + wire si; + sg13g2_nor2b_1 _3_ ( + .A(se), + .B_N(d), + .Y(_1_) + ); + sg13g2_a21oi_1 _4_ ( + .A1(si), + .A2(se), + .B1(_1_), + .Y(_0_) + ); + sg13g2_dfrbp_1 _5_ ( + .CLK(clk), + .D(_0_), + .Q(_2_), + .Q_N(q), + .RESET_B(nset) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffsqn.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffsqn.v new file mode 100644 index 00000000..cc865d08 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_sdffsqn.v @@ -0,0 +1,61 @@ +// //############################################################################# +// //# Function: Positive edge-triggered static inverting D-type flop-flop with # +// // async active low set and scan input # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_sdffsqn #( +// parameter PROP = "DEFAULT" +// ) ( +// input d, +// input si, +// input se, +// input clk, +// input nset, +// output reg qn +// ); +// +// always @(posedge clk or negedge nset) +// if (!nset) qn <= 1'b0; +// else qn <= se ? ~si : ~d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_sdffsqn(d, si, se, clk, nset, qn); + wire _0_; + wire _1_; + wire _2_; + input clk; + wire clk; + input d; + wire d; + input nset; + wire nset; + output qn; + wire qn; + input se; + wire se; + input si; + wire si; + sg13g2_nand2b_1 _3_ ( + .A_N(si), + .B(se), + .Y(_1_) + ); + sg13g2_o21ai_1 _4_ ( + .A1(d), + .A2(se), + .B1(_1_), + .Y(_0_) + ); + sg13g2_dfrbp_1 _5_ ( + .CLK(clk), + .D(_0_), + .Q(qn), + .Q_N(_2_), + .RESET_B(nset) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_tiehi.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_tiehi.v new file mode 100644 index 00000000..6f00afc5 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_tiehi.v @@ -0,0 +1,25 @@ +// //############################################################################# +// //# Function: Tie High Cell # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_tiehi #( +// parameter PROP = "DEFAULT" +// ) ( +// output z +// ); +// +// assign z = 1'b1; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_tiehi(z); + output z; + wire z; + sg13g2_tiehi _0_ ( + .L_HI(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_tielo.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_tielo.v new file mode 100644 index 00000000..8217e941 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_tielo.v @@ -0,0 +1,25 @@ +// //############################################################################# +// //# Function: Tie Low Cell # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_tielo #( +// parameter PROP = "DEFAULT" +// ) ( +// output z +// ); +// +// assign z = 1'b0; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_tielo(z); + output z; + wire z; + sg13g2_tielo _0_ ( + .L_LO(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xnor2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xnor2.v new file mode 100644 index 00000000..ae4739ac --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xnor2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2-Input Exclusive-Nor Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_xnor2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = ~(a ^ b); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_xnor2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_xnor2_1 _0_ ( + .A(b), + .B(a), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xnor3.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xnor3.v new file mode 100644 index 00000000..6bc007f8 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xnor3.v @@ -0,0 +1,42 @@ +// //############################################################################# +// //# Function: 3-Input Exclusive-Nor Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_xnor3 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// output z +// ); +// +// assign z = ~(a ^ b ^ c); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_xnor3(a, b, c, z); + wire _0_; + input a; + wire a; + input b; + wire b; + input c; + wire c; + output z; + wire z; + sg13g2_xor2_1 _1_ ( + .A(a), + .B(c), + .X(_0_) + ); + sg13g2_xnor2_1 _2_ ( + .A(b), + .B(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xnor4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xnor4.v new file mode 100644 index 00000000..7b986fa4 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xnor4.v @@ -0,0 +1,51 @@ +// //############################################################################# +// //# Function: 4-Input Exclusive-Nor Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_xnor4 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// input d, +// output z +// ); +// +// assign z = ~(a ^ b ^ c ^ d); +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_xnor4(a, b, c, d, z); + wire _0_; + wire _1_; + input a; + wire a; + input b; + wire b; + input c; + wire c; + input d; + wire d; + output z; + wire z; + sg13g2_xnor2_1 _2_ ( + .A(c), + .B(d), + .Y(_0_) + ); + sg13g2_xnor2_1 _3_ ( + .A(b), + .B(a), + .Y(_1_) + ); + sg13g2_xnor2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xor2.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xor2.v new file mode 100644 index 00000000..d71f5b95 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xor2.v @@ -0,0 +1,33 @@ +// //############################################################################# +// //# Function: 2-Input Exclusive-Or Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_xor2 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// output z +// ); +// +// assign z = a ^ b; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_xor2(a, b, z); + input a; + wire a; + input b; + wire b; + output z; + wire z; + sg13g2_xor2_1 _0_ ( + .A(b), + .B(a), + .X(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xor3.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xor3.v new file mode 100644 index 00000000..bf26a849 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xor3.v @@ -0,0 +1,42 @@ +// //############################################################################# +// //# Function: 3-Input XOR Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_xor3 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// output z +// ); +// +// assign z = a ^ b ^ c; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_xor3(a, b, c, z); + wire _0_; + input a; + wire a; + input b; + wire b; + input c; + wire c; + output z; + wire z; + sg13g2_xnor2_1 _1_ ( + .A(a), + .B(c), + .Y(_0_) + ); + sg13g2_xnor2_1 _2_ ( + .A(b), + .B(_0_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xor4.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xor4.v new file mode 100644 index 00000000..62ec8fbb --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/lambda/stdlib/la_xor4.v @@ -0,0 +1,51 @@ +// //############################################################################# +// //# Function: 4-Input XOR Gate # +// //# Copyright: Lambda Project Authors. All rights Reserved. # +// //# License: MIT (see LICENSE file in Lambda repository) # +// //############################################################################# +// +// module la_xor4 #( +// parameter PROP = "DEFAULT" +// ) ( +// input a, +// input b, +// input c, +// input d, +// output z +// ); +// +// assign z = a ^ b ^ c ^ d; +// +// endmodule + +/* Generated by Yosys 0.40+33 (git sha1 cd1fb8b15, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module la_xor4(a, b, c, d, z); + wire _0_; + wire _1_; + input a; + wire a; + input b; + wire b; + input c; + wire c; + input d; + wire d; + output z; + wire z; + sg13g2_xor2_1 _2_ ( + .A(c), + .B(d), + .X(_0_) + ); + sg13g2_xnor2_1 _3_ ( + .A(b), + .B(a), + .Y(_1_) + ); + sg13g2_xnor2_1 _4_ ( + .A(_0_), + .B(_1_), + .Y(z) + ); +endmodule diff --git a/lambdapdk/ihp130/libs/sg13g2_stdcell/techmap/yosys/cells_latch.v b/lambdapdk/ihp130/libs/sg13g2_stdcell/techmap/yosys/cells_latch.v new file mode 100644 index 00000000..fd4bffe8 --- /dev/null +++ b/lambdapdk/ihp130/libs/sg13g2_stdcell/techmap/yosys/cells_latch.v @@ -0,0 +1,15 @@ +module $_DLATCH_P_(input E, input D, output Q); + sg13g2_dlhq_1 _TECHMAP_REPLACE_ ( + .D(D), + .GATE(E), + .Q(Q) + ); +endmodule + +module $_DLATCH_N_(input E, input D, output Q); + sg13g2_dlhq_1 _TECHMAP_REPLACE_ ( + .D(D), + .GATE(~E), + .Q(Q) + ); +endmodule diff --git a/pyproject.toml b/pyproject.toml index bd957185..e9948c7e 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -22,7 +22,7 @@ version = {attr = "lambdapdk.__version__"} [tool.pytest.ini_options] testpaths = "tests" -timeout = "60" +timeout = "180" [project.optional-dependencies] # Test dependencies. diff --git a/scripts/generate_lamdbalib.py b/scripts/generate_lamdbalib.py index 9109f4e8..3c049675 100755 --- a/scripts/generate_lamdbalib.py +++ b/scripts/generate_lamdbalib.py @@ -17,7 +17,8 @@ skywater130_demo, asap7_demo, freepdk45_demo, - gf180_demo + gf180_demo, + ihp130_demo ) pdk_root = os.path.dirname(os.path.dirname(os.path.abspath(__file__))) @@ -51,6 +52,12 @@ "asap7sc7p5t_slvt" ] }, + "ihp130": { + "target": ihp130_demo, + "libs": [ + "sg13g2_stdcell" + ] + } } @@ -268,7 +275,30 @@ def auxlib(verible_bin): 'la_tbuf' ] }, - } + }, + "ihp130": { + "sg13g2_stdcell": { + "implemented": [ + 'la_antenna', + 'la_clkicgand', + 'la_clkicgor', + 'la_pwrbuf', + 'la_tbuf', + 'la_dsync', + 'la_rsync' + ], + "missing": [ + 'la_decap', + 'la_footer', + 'la_header', + 'la_ibuf', + 'la_idiff', + 'la_keeper', + 'la_obuf', + 'la_odiff' + ] + } + }, } procs = [] @@ -363,6 +393,26 @@ def ramlib(verible_bin): ("dout1", "mem_dout"), ] + ihp130_spram_port_map = [ + ("A_CLK", "clk"), + ("A_MEN", "~ce_in"), + ("A_WEN", "~we_in"), + ("A_REN", "we_in"), + ("A_ADDR", "mem_addr"), + ("A_DIN", "mem_din"), + ("A_DLY", "1'b1"), + ("A_DOUT", "mem_dout"), + ("A_BM", "mem_wmask"), + ("A_BIST_CLK", "1'b0"), + ("A_BIST_EN", "1'b0"), + ("A_BIST_MEN", "1'b0"), + ("A_BIST_WEN", "1'b0"), + ("A_BIST_REN", "1'b0"), + ("A_BIST_ADDR", "'b0"), + ("A_BIST_DIN", "'b0"), + ("A_BIST_BM", "'b0") + ] + srams = { "asap7": { "name": "fakeram7", @@ -439,6 +489,30 @@ def ramlib(verible_bin): } } }, + "ihp130": { + "name": "sg13g2_sram", + "implementations": ["la_spram"], + "la_spram": { + "RM_IHPSG13_1P_1024x64_c2_bm_bist": { + "DW": 64, "AW": 10, "port_map": ihp130_spram_port_map + }, + "RM_IHPSG13_1P_2048x64_c2_bm_bist": { + "DW": 64, "AW": 11, "port_map": ihp130_spram_port_map + }, + "RM_IHPSG13_1P_256x48_c2_bm_bist": { + "DW": 48, "AW": 8, "port_map": ihp130_spram_port_map + }, + "RM_IHPSG13_1P_256x64_c2_bm_bist": { + "DW": 64, "AW": 8, "port_map": ihp130_spram_port_map + }, + "RM_IHPSG13_1P_512x64_c2_bm_bist": { + "DW": 64, "AW": 9, "port_map": ihp130_spram_port_map + }, + "RM_IHPSG13_1P_64x64_c2_bm_bist": { + "DW": 64, "AW": 6, "port_map": ihp130_spram_port_map + }, + } + }, } for pdk, info in srams.items(): diff --git a/tests/test_getters.py b/tests/test_getters.py index 7e7e381f..9316d78f 100644 --- a/tests/test_getters.py +++ b/tests/test_getters.py @@ -2,14 +2,15 @@ from siliconcompiler import Chip import lambdapdk -from lambdapdk import asap7, freepdk45, sky130, gf180 +from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130 from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7, fakeio7 from lambdapdk.freepdk45.libs import nangate45, fakeram45 from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram +from lambdapdk.ihp130.libs import sg13g2_stdcell, sg13g2_sram -@pytest.mark.parametrize('pdk', [asap7, freepdk45, sky130, gf180]) +@pytest.mark.parametrize('pdk', [asap7, freepdk45, sky130, gf180, ihp130]) def test_pdk(pdk): chip = Chip('') chip.use(pdk) @@ -22,7 +23,8 @@ def test_pdk(pdk): asap7sc7p5t, fakeram7, fakeio7, # asap7 nangate45, fakeram45, # freepdk45 sky130sc, sky130io, sky130sram, # sky130 - gf180mcu, gf180io, gf180sram # gf180 + gf180mcu, gf180io, gf180sram, # gf180 + sg13g2_stdcell, sg13g2_sram # ihp130 ]) def test_lib(lib): chip = Chip('') diff --git a/tests/test_lambda.py b/tests/test_lambda.py index 465a80c7..b767ad6c 100644 --- a/tests/test_lambda.py +++ b/tests/test_lambda.py @@ -6,13 +6,15 @@ from lambdapdk.freepdk45.libs import nangate45, fakeram45 from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram +from lambdapdk.ihp130.libs import sg13g2_stdcell, sg13g2_sram @pytest.mark.parametrize('module,path', [ (asap7sc7p5t, 'lambdapdk/asap7/libs/{lib_name}/lambda/auxlib'), (nangate45, 'lambdapdk/freepdk45/libs/{lib_name}/lambda/auxlib'), (sky130sc, 'lambdapdk/sky130/libs/{lib_name}/lambda/auxlib'), - (gf180mcu, 'lambdapdk/gf180/libs/{lib_name}/lambda/auxlib') + (gf180mcu, 'lambdapdk/gf180/libs/{lib_name}/lambda/auxlib'), + (sg13g2_stdcell, 'lambdapdk/ihp130/libs/{lib_name}/lambda/auxlib') ]) def test_la_auxlib(module, path): libs = module.setup() @@ -29,7 +31,8 @@ def test_la_auxlib(module, path): (asap7sc7p5t, 'lambdapdk/asap7/libs/{lib_name}/lambda/stdlib'), (nangate45, 'lambdapdk/freepdk45/libs/{lib_name}/lambda/stdlib'), (sky130sc, 'lambdapdk/sky130/libs/{lib_name}/lambda/stdlib'), - (gf180mcu, 'lambdapdk/gf180/libs/{lib_name}/lambda/stdlib') + (gf180mcu, 'lambdapdk/gf180/libs/{lib_name}/lambda/stdlib'), + (sg13g2_stdcell, 'lambdapdk/ihp130/libs/{lib_name}/lambda/stdlib') ]) def test_la_stdlib(module, path): libs = module.setup() @@ -47,6 +50,7 @@ def test_la_stdlib(module, path): 'lambdapdk/freepdk45/libs/fakeram45/lambda', 'lambdapdk/sky130/libs/sky130sram/lambda', 'lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda', + 'lambdapdk/ihp130/libs/sg13g2_sram/lambda', ]) def test_la_ramlib(path): assert lambdalib.check(path, 'ramlib') @@ -65,7 +69,8 @@ def test_la_iolib(path): asap7sc7p5t, fakeram7, nangate45, fakeram45, gf180mcu, gf180io, gf180sram, - sky130sc, sky130io, sky130sram + sky130sc, sky130io, sky130sram, + sg13g2_stdcell, sg13g2_sram ]) def test_lambdalib_is_present(module): chip = Chip('') diff --git a/tests/test_paths.py b/tests/test_paths.py index 80bc585b..f12171b0 100644 --- a/tests/test_paths.py +++ b/tests/test_paths.py @@ -2,14 +2,16 @@ from siliconcompiler import Chip import os -from lambdapdk import asap7, freepdk45, sky130, gf180 +from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130 from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7, fakeio7 from lambdapdk.freepdk45.libs import nangate45, fakeram45 from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram +from lambdapdk.ihp130.libs import sg13g2_stdcell -@pytest.mark.parametrize('pdk', [asap7, freepdk45, sky130, gf180]) +@pytest.mark.parametrize('pdk', [ + asap7, freepdk45, sky130, gf180, ihp130]) def test_pdk_paths(pdk): chip = Chip('') chip.use(pdk) @@ -20,7 +22,8 @@ def test_pdk_paths(pdk): asap7sc7p5t, fakeram7, fakeio7, # asap7 nangate45, fakeram45, # freepdk45 sky130sc, sky130io, sky130sram, # sky130 - gf180mcu, gf180io, gf180sram # gf180 + gf180mcu, gf180io, gf180sram, # gf180 + sg13g2_stdcell # ihp130 ]) def test_lib_paths(lib): chip = Chip('')