This repository contains Verilog code and associated problem statements for each of the 8 weeks of laboratory exercises completed during the third semester as part of the course: DDCO.
The repository is organized into weekly folders. Each weekly folder contains:
- README.md: Describes the problem statements for the week.
- Verilog Files (.v): Contains the Verilog source code for the laboratory exercises.
Feel free to contribute by submitting issues for any bugs or improvements. I hope this serves as a valuable resource for your learning and projects in DDCO.
