replaced module name with my own

stevej · Sep 25, 2024 · 23230dd · 23230dd
1 parent 7d983d3
commit 23230dd
Showing 1 changed file with 1 addition and 3 deletions.
diff --git a/test/tb.v b/test/tb.v
@@ -27,9 +27,7 @@ module tb ();
   wire VGND = 1'b0;
 `endif
 
-  // Replace tt_um_example with your module name:
-  tt_um_example user_project (
-
+tt_um_jtag_example_stevej user_project (
       // Include power ports for the Gate Level test:
 `ifdef GL_TEST
       .VPWR(VPWR),