timescale and comments

src/jtag.v

@@ -2,6 +2,7 @@
 `define _JTAG_
 
 `default_nettype none
+`timescale 1us / 100 ns
 
 `include "byte_transmitter.v"
 

src/minipit.v

@@ -1,6 +1,9 @@
 `ifndef _MINIPIT_
 `define _MINIPIT_
 
+`default_nettype none
+`timescale 1us / 100 ns
+
 module minipit (
     input clk,
     input rst_n,

test/test.py

@@ -54,7 +54,7 @@ async def test_rms_five_high_for_reset(dut):
         dut.ui_in.value = 0b0000_0111
         await ClockCycles(dut.clk, 1)
         dut.ui_in.value = 0b0000_0110
-        # At this point, the design is in reset but 
+        # At this point, the design is in reset but
         # the interrupt is also firing on all the other pins.
         assert dut.uo_out.value == 0xFE