From 934195b54a28b23660e40f311a7d9cbc521f1f25 Mon Sep 17 00:00:00 2001
From: Steve Jenson <stevej@gmail.com>
Date: Thu, 24 Oct 2024 14:37:08 -0700
Subject: [PATCH] timescale and comments

---
 src/jtag.v    | 1 +
 src/minipit.v | 3 +++
 test/test.py  | 2 +-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/jtag.v b/src/jtag.v
index eb2befd..72c53af 100644
--- a/src/jtag.v
+++ b/src/jtag.v
@@ -2,6 +2,7 @@
 `define _JTAG_
 
 `default_nettype none
+`timescale 1us / 100 ns
 
 `include "byte_transmitter.v"
 
diff --git a/src/minipit.v b/src/minipit.v
index f497885..b8041c8 100644
--- a/src/minipit.v
+++ b/src/minipit.v
@@ -1,6 +1,9 @@
 `ifndef _MINIPIT_
 `define _MINIPIT_
 
+`default_nettype none
+`timescale 1us / 100 ns
+
 module minipit (
     input clk,
     input rst_n,
diff --git a/test/test.py b/test/test.py
index de2d27d..d730e80 100644
--- a/test/test.py
+++ b/test/test.py
@@ -54,7 +54,7 @@ async def test_rms_five_high_for_reset(dut):
         dut.ui_in.value = 0b0000_0111
         await ClockCycles(dut.clk, 1)
         dut.ui_in.value = 0b0000_0110
-        # At this point, the design is in reset but 
+        # At this point, the design is in reset but
         # the interrupt is also firing on all the other pins.
         assert dut.uo_out.value == 0xFE