04-Sep-2024
- Support for NVC Simulator
- NVC simulator can be started passing the argument "--nvc" to the run.py
- Added NVC simulator to CI scripts
- Co-authored by nickg
- Questa integration
- Script to automatically compile all Open Logic features in Questa
- Questa tutorial (VHDL and Verilog)
- Addition of to01() functions to olo_base_pkg_logic
- olo_intf_spi_slave
- SPI slave
- olo_base_cc_handshake
- Clock crossing with fully Read/Valid handshake but without need for distributed RAM (in contrast to olo_base_fifo_async)
- Various documentation improvements
- Various optimizations on the CI/CD infrastructure
- Reduction of the latency of olo_base_cc_pulse by one clock cycle
- None
- None
30-Jul-2024
- Efinix Efinity integration
- Script to automatically import all Open Logic features into an Efinity project
- Addition of synthesis attributes for Efinity
- Efinity tutorial
- Added FuseSoC package manager support
- olo_intf_spi_master
- SPI master
- Various documentation improvements
- Various optimizations on the CI/CD infrastructure
- None
- Fixed sensitivity list in olo_axi_master_simple (#41)
- M_Axi_RResp was missing
- Credits to kuriousd for reporting
- Process scoped constraints late for AMD Vivado
- User constraints must be processed before scoped constraints, otherwise clocks are not known to scoped constraints
- None
06-Jul-2024
-
Altera Quartus integration
- Script to automatically import all Open Logic features into a Quartus project
-
Added tutorials
- Vivado Verilog tutorial
- Quartus VHDL tutorial
- Quartus Verilog tutorial
-
olo_base_reset_gen
- Reset generator (and synchronizer)
-
olo_base_flowctrl_handler
- Allows to add flow-control (ready) around entities without flow-control (valid only)
- Various documentation improvements
- Removed t_aslv (array of unconstrained std_logic_vector) from olo_base_pkg_array
- Arrays of unconstrained types are not accepted by Quartus
- None
27-Jun-2024
- AMD Vivado integration
- Script to automatically import all Open Logic features into a Vivado project
- Vivado tutorial
- olo_intf_clk_meas
- Measure the frequency of a clock signal (based on a clock with a known frequency)
- olo_intf_debounce
- Debouncing for external signals (e.g. inputs from switches or buttons)
- Various documentation improvements
- Execute scoped constraint scripts in separate namespaces
- This avoids unwanted interactions between the script through global variables
- None
- Fix scoped constraints for olo_intf_sync
- Incomplete input delays were reported before the fix
- Fix inconsistencies of olo_intf_i2c_master generic default values compared to documentation
- There was a mismatch for CmdTimeout_g
- ClkFrequency_g had a default value in the implementation before the change (which is wrong because the clock is specific to the design)
15-Jun-2024
- olo_intf_i2c_master
- I2C master
- Multi-Master and clock-stretching capable
- olo_intf_sync
- Double stage synchronizer for asynchronous external signals
- Includes scoped timing constraints
- olo_axi_master_full
- AXI Master with support for unaligned and odd-sized transfers (other sizes than multiple of AXI words)
- Various documentation improvements
- Added Rd_Last signal to olo_axi_master_simple to simplify handling of read-data.
- olo_base_wconv_n2xn now supports InWidth=OutWidth
- None
- Change default UserTransactionSizeBits_g in olo_axi_master_simple to 24 bits
- The combination of default values before was illegal
- Backwards compatible because the default values had to be overwritten for successful compilation before the change anyways.
- Change default values of AlmFullLevel_g and AlmEmptyLevel_g to 0
- Using another generic (Depth_g) as default value for generics is illegal.
- Backwards compatible because the default values had to be overwritten for successful compilation before the change anyways.
- Fix AxiDataWidth_g related assertions in olo_axi_lite_slave
- Backwards compatible because the change only adds error messages for anyways illegal generics combinations
31-May-2024
First release
n/a
n/a
n/a
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All 0.x.x releases are considered early stage development and not documented in detail.