EntityList.md

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Entity List

Note that components are split into categories.

base

Packages (olo_base_pkg_<...>)

Packages with type declarations and functions used in Open Logic internally or on its interfaces.

Package	Description
olo_base_pkg_array	Array type definitions (e.g. arrays of std_logic_vector)
olo_base_pkg_math	Mathematic functions (e.g. log2)
olo_base_pkg_logic	Mathematic functions (e.g. binaryToGray)

Clock Crossings (olo_base_cc_<...>)

Clock crossings are a key topic and they all follow the same clock crossing principles.

Entity	Description
olo_base_cc_reset	Synchronization of resets between two clock domains (bi-directional)
olo_base_cc_bits	Transfer a group of individual single bit signals from one clock domain to another clock domain
olo_base_cc_pulse	Transfer single-cycle pulses from one clock domain to another clock domain
olo_base_cc_simple	Transfer selectively valid data from one clock domain to another clock domain (data/valid pair)
olo_base_cc_status	Transfer status and configuration information from one clock domain to another clock domain. The update rate is relatively low but consistency is guaranteed
olo_base_cc_n2xn	Transfer data from a slower clock to a faster phase aligned clock (output clock frequency is an exact integer multiple of the input clock frequency and the clocks are phase aligned).
olo_base_cc_xn2n	Transfer data from a faster clock to a slower phase aligned clock (input clock frequency is an exact integer multiple of the output clock frequency and the clocks are phase aligned).
olo_base_cc_handshake	Transfer data from one clock domain to another clock domain using the standard Valid/Ready handshaking. For technologies with distributed RAM (LUT can be used as small RAM), olo_base_fifo_async in most cases is preferred over this entity.
olo_base_fifo_async	Asynchronous FIFO (separate write and read clocks) This is not a pure clock-crossing entity but it can be used as such.

RAM Implementations (olo_base_ram_<...>)

Entity	Description
olo_base_ram_sp	Single port RAM
olo_base_ram_sdp	Simple dual-port RAM
olo_base_ram_tdp	True dual-port RAM

FIFO Implementations (olo_base_fifo_<...>)

Entity	Description
olo_base_fifo_sync	Synchronous FIFO (single clock)
olo_base_fifo_async	Asynchronous FIFO (separate write and read clocks)

Width Conversions (olo_base_wconv_<...>)

Entity	Description
olo_base_wconv_n2xn	Increase word width by an integer factor (OutWidth = InWidth x N) Convert from TDM to parallel (see Conventions)
olo_base_wconv_xn2n	Decrease word width by an integer factor (OutWidth = InWidth / N) Convert from parallel to TDM (see Conventions)

Arbiters (olo_base_arb_<...>)

Entity	Description
olo_base_arb_prio	Priority arbiter - Always selects the highest priority requester with a pending request.
olo_base_arb_rr	Round robin arbiter - iterate through all requesters with a pending request.

TDM (olo_base_tdm_<...>)

See Conventions for a description about TDM (time-division-multiplexing).

Entity	Description
olo_base_tdm_mux	Select one specific channel from a TDM signal.
olo_base_wconv_n2xn	Convert from TDM to parallel (see Conventions) This is not a pure TDM entity but it can be used for TDM purposes.
olo_base_wconv_xn2n	Convert from parallel to TDM (see Conventions) This is not a pure TDM entity but it can be used for TDM purposes.

Miscellaneous

Entity	Description
olo_base_pl_stage	Implements one or more pipeline stages (register stages) - with or without support for backpressure (Ready)
olo_base_delay	Fixed duration delay (fixed number of data-beats)
olo_base_delay_cfg	Configurable duration delay (runtime configurable number of data-beats)
olo_base_dyn_sft	Dynamic barrel shifter (number of bits to shift is configurable per sample at runtime)
olo_base_prbs	PRBS (pseudo random binary sequence) generator based on linear feedback shift register (LFSR) implementation.
olo_base_strobe_gen	Strobe generator. Generate pulses at a fixed frequency
olo_base_strobe_div	Strobe divider. Only forward every N'th pulse (divide event frequency). Can also be used to convert single-cycle pulses to acknowledged events (pulse stays active until acknowledged).
olo_base_reset_gen	Reset generator - Generates reset pulses of specified duration after configuration and upon request
olo_base_flowctrl_handler	Inplements full flow-control (including Ready/back-pressure) around processing entities that do not support Ready/back-pressure natively.

axi

Entity	Description
olo_axi_pl_stage	Implements a AXI4 pipeline stage, registering all signals of an AXI4 interface. Can be used for AXI4-Lite as well.
olo_axi_lite_slave	Interface to attach user register banks and memories to the AXI4-Lite bus.
olo_axi_master_simple	AXI4 master - does execute arbitrarily sized transfer over AXI4. The _simple version of the master does only allow access to word-aligned addresses and sizes.
olo_axi_master_full	AXI4 master - Same as olo_axi_master_simple but does allow access that are not word-aligned (in terms of start address, size or both).

Note: Open Logic focuses on providing utilities for development of AXI endpoints (masters and slaves). Open Logic does not aim to provide AXI interconnect infrastructure (e.g. crossbars, interconnects, ...). Often the vendor IPs are used (for tool integration reasons) for these aspects. If you are looking for a pure VHDL implementation of AXI interconnects, it's suggested that you use one of the following libraries:

• hdl-modules
  • hdl-modules utilizes VHDL-2008 which has limited support in some tools (namely the Standard and Lite versions of Quartus Prime)
  • hdl-modules currently does only contain synthesis attributes for AMD (Vivado)
• SURF
  • SURF currently does only target AMD (Vivado) and Altera (Quartus Prime)

intf

Entity	Description
olo_intf_sync	Double stage synchronizer for external signals.
olo_intf_i2c_master	I2C Master - Supports the full standard including arbitration (multi-master I2C) and clock stretching.
olo_intf_spi_master	SPI Master - Supports handling multiple slaves and variable width transactions as well as all clock phases and poloarities and LSB/MSB first.
olo_intf_spi_slave	SPI Slave - Supports all clock phases and poloarities and LSB/MSB first.
olo_intf_debounce	Debouncer (for bouncing signals from buttons and switches) - Includes double-stage synchronizers.
olo_intf_clk_meas	Measure the frequency of a clock.