VHDL Source: olo_base_flowctrl_handler
This component implements full flow-control (including Ready/back-pressure) around processing entities that do not support Ready/back-pressure natively.
The usage is depicted below:
The olo_base_flowctrl_handler includes a small FIFO buffer and ensures to de-assert In_Ready in a way that remaining output samples from processing can be absorbed without data-loss when Out_Ready is de-asserted. The FIFO buffer is chosen large enough to provide full throughput (i.e. not add any needless stall-cycles).
For processing entities that do not even provide the handling of the Valid flag, the Valid flag handling can easily be implemented by adding an olo_base_delay component with the same delay as the processing itself:
| Name | Type | Default | Description |
|---|---|---|---|
| InWidth_g | positive | - | Data width on the input side (input to processing) |
| OutWidth_g | positive | - | Data width on the output side (output from processing) |
| SamplesToAbsorb_g | positive | - | Maximum number of samples that the processing may produce after ToProc_Valid was de-asserted. For processing without rate changes (simple processing pipelines) this is the number of pipeline stages in processing. For processing with rate changes the value depends on the exact implementation and behavior of the processing. Note: A too high value is never a problem (except for resource usage). When in doubt, round the number up to a value that is for sure large enough. |
| RamStyle_g | boolean | true | Through this generic, the exact resource to use for implementation can be controlled. For details refer to the description in olo_base_ram_sdp. |
| RamBehavior_g | string | "RBW" | "RBW" = read-before-write, "WBR" = write-before-read For details refer to the description in olo_base_ram_sdp. |
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_Data | in | Width_g | - | Input data |
| In_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for In_Data |
| In_Ready | out | 1 | N/A | AXI4-Stream handshaking signal for In_Data |
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Data | out | Width_g | N/A | Output data |
| Out_Valid | out | 1 | N/A | AXI4-Stream handshaking signal for Out_Data |
| Out_Ready | in | 1 | '1' | AXI4-Stream handshaking signal for Out_Data |
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| ToProc_Data | out | Width_g | N/A | Input data to processing |
| ToProc_Valid | out | 1 | N/A | AXI4-Stream handshaking signal for ToProc_Data |
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| FromProc_Data | in | Width_g | - | Output data from processing |
| FromProc_Valid | in | 1 | - | AXI4-Stream handshaking signal for FromProc_Data |
The architecture of the entity is depicted below:
The depth of the FIFO is configured as (SamplesToAbsorb_g+2)*2.
The theoretical formula is (SamplesToAbsorb_g+LatencyFIFO+1)*2 where the FIFO Latency of the olo_base_sync_fifo is 1.