From de9f590bd41fa40909e4a8c8384b94225713b329 Mon Sep 17 00:00:00 2001 From: Richard Meadows <962920+richardeoin@users.noreply.github.com> Date: Sat, 1 Jul 2023 13:48:20 +0200 Subject: [PATCH 1/4] Remove unnecessary borrows in unsafe register write expressions --- src/pwr.rs | 6 ++---- src/sai/mod.rs | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/pwr.rs b/src/pwr.rs index decc4143..69d40046 100644 --- a/src/pwr.rs +++ b/src/pwr.rs @@ -510,11 +510,9 @@ impl Pwr { ))] if matches!(self.target_vos, VoltageScale::Scale0) { unsafe { - &(*RCC::ptr()).apb4enr.modify(|_, w| w.syscfgen().enabled()) - }; - unsafe { - &(*SYSCFG::ptr()).pwrcr.modify(|_, w| w.oden().set_bit()) + (*RCC::ptr()).apb4enr.modify(|_, w| w.syscfgen().enabled()) }; + unsafe { (*SYSCFG::ptr()).pwrcr.modify(|_, w| w.oden().set_bit()) }; while d3cr!(self.rb).read().vosrdy().bit_is_clear() {} vos = VoltageScale::Scale0; } diff --git a/src/sai/mod.rs b/src/sai/mod.rs index de5819f2..381ab334 100644 --- a/src/sai/mod.rs +++ b/src/sai/mod.rs @@ -288,7 +288,7 @@ macro_rules! sai_hal { /// e.g. for SAI1 1-3 are valid and 0 is invalid pub fn set_sync_input(&mut self, selection: u8) { assert!(selection < 0b1_00); - unsafe { &self.rb.gcr.modify(|_, w| w.syncout().bits(selection)) }; + unsafe { self.rb.gcr.modify(|_, w| w.syncout().bits(selection)) }; } /// Synchronization output for other SAI blocks From 085b9a87c426a40cfbe16b1b6363297e549c2349 Mon Sep 17 00:00:00 2001 From: Richard Meadows <962920+richardeoin@users.noreply.github.com> Date: Sat, 1 Jul 2023 13:55:08 +0200 Subject: [PATCH 2/4] Simplify cfg expressions --- src/pwr.rs | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/pwr.rs b/src/pwr.rs index 69d40046..5f9258c6 100644 --- a/src/pwr.rs +++ b/src/pwr.rs @@ -98,7 +98,7 @@ impl PwrExt for PWR { fn constrain(self) -> Pwr { Pwr { rb: self, - #[cfg(any(feature = "smps"))] + #[cfg(feature = "smps")] supply_configuration: SupplyConfiguration::Default, target_vos: VoltageScale::Scale1, backup_regulator: false, @@ -111,7 +111,7 @@ impl PwrExt for PWR { /// Generated by calling `constrain` on the PAC's PWR peripheral. pub struct Pwr { pub(crate) rb: PWR, - #[cfg(any(feature = "smps"))] + #[cfg(feature = "smps")] supply_configuration: SupplyConfiguration, target_vos: VoltageScale, backup_regulator: bool, @@ -157,7 +157,7 @@ impl PowerConfiguration { /// SMPS Supply Configuration - Dual Core parts /// /// Refer to RM0399 Rev 3 Table 32. -#[cfg(any(feature = "smps"))] +#[cfg(feature = "smps")] enum SupplyConfiguration { Default = 0, LDOSupply, @@ -168,7 +168,7 @@ enum SupplyConfiguration { Bypass, } -#[cfg(any(feature = "smps"))] +#[cfg(feature = "smps")] macro_rules! supply_configuration_setter { ($($config:ident: $name:ident, $doc:expr,)*) => { $( @@ -265,7 +265,7 @@ pub(crate) fn current_vos() -> VoltageScale { /// Internal power methods impl Pwr { /// Verify that the lower byte of CR3 reads as written - #[cfg(any(feature = "smps"))] + #[cfg(feature = "smps")] fn verify_supply_configuration(&self) { use SupplyConfiguration::*; let error = "Values in lower byte of PWR.CR3 do not match the \ @@ -367,7 +367,7 @@ impl Pwr { /// Builder methods impl Pwr { - #[cfg(any(feature = "smps"))] + #[cfg(feature = "smps")] supply_configuration_setter! { LDOSupply: ldo, "VCORE power domains supplied from the LDO. \ LDO voltage adjusted by VOS. \ @@ -449,7 +449,7 @@ impl Pwr { w.scuen().set_bit().ldoen().set_bit().bypass().clear_bit() }); - #[cfg(any(feature = "smps"))] + #[cfg(feature = "smps")] self.rb.cr3.modify(|_, w| { use SupplyConfiguration::*; @@ -481,7 +481,7 @@ impl Pwr { }); // Verify supply configuration, panics if these values read // from CR3 do not match those written. - #[cfg(any(feature = "smps"))] + #[cfg(feature = "smps")] self.verify_supply_configuration(); // Validate the supply configuration. If you are stuck here, it is From ca203f37d98325ff045c3b5b102efbdf8b0ae273 Mon Sep 17 00:00:00 2001 From: Richard Meadows <962920+richardeoin@users.noreply.github.com> Date: Sat, 1 Jul 2023 13:55:31 +0200 Subject: [PATCH 3/4] Use new default syntax --- src/adc.rs | 8 ++------ src/dma/mdma.rs | 24 ++++++------------------ src/dma/mod.rs | 8 ++------ src/rcc/rec.rs | 8 ++------ 4 files changed, 12 insertions(+), 36 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index 5f1310ae..f07391c1 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -89,7 +89,7 @@ pub enum AdcDmaMode { /// Options for the sampling time, each is T + 0.5 ADC clock cycles. // // Refer to RM0433 Rev 7 - Chapter 25.4.13 -#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[derive(Default, Clone, Copy, Debug, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[allow(non_camel_case_types)] pub enum AdcSampleTime { @@ -102,6 +102,7 @@ pub enum AdcSampleTime { /// 16.5 cycles sampling time T_16, /// 32.5 cycles sampling time + #[default] T_32, /// 64.5 cycles sampling time T_64, @@ -111,11 +112,6 @@ pub enum AdcSampleTime { T_810, } -impl Default for AdcSampleTime { - fn default() -> Self { - AdcSampleTime::T_32 - } -} impl AdcSampleTime { /// Returns the number of half clock cycles represented by this sampling time fn clock_cycles_x2(&self) -> u32 { diff --git a/src/dma/mdma.rs b/src/dma/mdma.rs index ca74d979..52d884fb 100644 --- a/src/dma/mdma.rs +++ b/src/dma/mdma.rs @@ -208,11 +208,12 @@ impl MdmaSize { } /// MDMA increment mode -#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[derive(Default, Debug, Clone, Copy, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MdmaIncrement { Fixed, /// Increment by one source/destination element each element + #[default] Increment, /// Decrement by one source/destination element each element Decrement, @@ -225,11 +226,6 @@ pub enum MdmaIncrement { /// initialisation will panic DecrementWithOffset(MdmaSize), } -impl Default for MdmaIncrement { - fn default() -> Self { - MdmaIncrement::Increment - } -} /// MDMA burst size. This type contains the _register_ value, thus the burst /// size is equal to 2^N where N is the register value. @@ -278,10 +274,11 @@ impl defmt::Format for MdmaBurstSize { } /// MDMA Packing/Alignment mode -#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[derive(Default, Debug, Clone, Copy, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MdmaPackingAlignment { /// Source data is packed/unpacked into the destination data size + #[default] Packed, /// Source data is extended into the destination data size. Source data /// smaller than the destination is right-aligned and padded with zeros @@ -299,30 +296,21 @@ pub enum MdmaPackingAlignment { /// of the source is written to the destination. TruncateLeft, } -impl Default for MdmaPackingAlignment { - fn default() -> Self { - MdmaPackingAlignment::Packed - } -} /// MDMA trigger mode -#[derive(Debug, Clone, Copy)] +#[derive(Default, Debug, Clone, Copy)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MdmaTrigger { /// Each MDMA request triggers a buffer transfer Buffer = 0b00, /// Each MDMA request triggers a block transfer + #[default] Block = 0b01, /// Each MDMA request triggers a repeated block transfer (Not Supported) RepeatedBlock = 0b10, /// Each MDMA request triggers a linked-link transfer (Not Supported) LinkedList = 0b11, } -impl Default for MdmaTrigger { - fn default() -> Self { - MdmaTrigger::Block - } -} /// MDMA interrupts #[derive(Debug, Clone, Copy)] diff --git a/src/dma/mod.rs b/src/dma/mod.rs index a5d47b61..6359792d 100644 --- a/src/dma/mod.rs +++ b/src/dma/mod.rs @@ -272,23 +272,19 @@ pub mod config { /// the same software priority level, the stream with the lower number takes /// priority over the stream with the higher number. For example, Stream 2 /// takes priority over Stream 4. - #[derive(Debug, Clone, Copy)] + #[derive(Default, Debug, Clone, Copy)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Priority { /// Low priority. Low, /// Medium priority. + #[default] Medium, /// High priority. High, /// Very high priority. VeryHigh, } - impl Default for Priority { - fn default() -> Self { - Priority::Medium - } - } impl Bits for Priority { fn bits(self) -> u8 { diff --git a/src/rcc/rec.rs b/src/rcc/rec.rs index f7de20df..6b2390da 100644 --- a/src/rcc/rec.rs +++ b/src/rcc/rec.rs @@ -92,22 +92,18 @@ pub trait ResetEnable { /// The clock gating state of a peripheral in low-power mode /// /// See RM0433 rev 7. Section 8.5.11 -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Default, Copy, Clone, PartialEq, Eq)] pub enum LowPowerMode { /// Kernel and bus interface clocks are not provided in low-power modes. Off, /// Kernel and bus interface clocks are provided in CSleep mode. + #[default] Enabled, /// Kernel and bus interface clocks are provided in both CSleep and CStop /// modes. Only applies to peripherals in the D3 / SRD. If the peripheral is /// not in the D3 / SRD then this has the same effect as `Enabled`. Autonomous, } -impl Default for LowPowerMode { - fn default() -> Self { - LowPowerMode::Enabled - } -} impl Rcc { /// Returns all the peripherals resets / enables / kernel clocks. From e5dc056086af1aabb30ce4e1c3b34f11889855a6 Mon Sep 17 00:00:00 2001 From: Richard Meadows <962920+richardeoin@users.noreply.github.com> Date: Sat, 1 Jul 2023 14:23:09 +0200 Subject: [PATCH 4/4] Elide unnecessary explicit lifetime --- src/spi.rs | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/spi.rs b/src/spi.rs index 3e17819b..44edc11f 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -1170,9 +1170,7 @@ macro_rules! spi { } /// Internal implementation for blocking::spi::Write - fn transfer_internal_w<'w>(&mut self, - write_words: &'w [$TY], - ) -> Result<(), Error> { + fn transfer_internal_w(&mut self, write_words: &[$TY]) -> Result<(), Error> { use hal::spi::FullDuplex; // both buffers are the same length @@ -1230,9 +1228,7 @@ macro_rules! spi { } /// Internal implementation for blocking::spi::Transfer - fn transfer_internal_rw<'w>(&mut self, - words : &'w mut [$TY] - ) -> Result<(), Error> { + fn transfer_internal_rw(&mut self, words : &mut [$TY]) -> Result<(), Error> { use hal::spi::FullDuplex; if words.is_empty() {