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Merge pull request #119 from stnolting/dependabot/submodules/neorv32-…
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[Dependabot]: Bump neorv32 from `7e24fce` to `3d71f3e`
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stnolting authored Oct 1, 2024
2 parents 439dbf0 + d189291 commit 2f3a757
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Showing 3 changed files with 4 additions and 2 deletions.
1 change: 1 addition & 0 deletions .gitmodules
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[submodule "neorv32"]
path = neorv32
url = https://github.com/stnolting/neorv32
ignore = dirty
3 changes: 2 additions & 1 deletion src/neorv32_verilog_wrapper.vhd
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Expand Up @@ -28,10 +28,11 @@ begin
INT_BOOTLOADER_EN => true, -- boot configuration: boot explicit bootloader
-- RISC-V CPU Extensions --
RISCV_ISA_A => true, -- implement atomic memory operations extension?
RISCV_ISA_B => true, -- implement bit-manipulation extension?
RISCV_ISA_C => true, -- implement compressed extension?
RISCV_ISA_M => true, -- implement mul/div extension?
RISCV_ISA_U => true, -- implement user mode extension?
RISCV_ISA_Zba => true, -- implement shifted-add bit-manipulation extension
RISCV_ISA_Zbb => true, -- implement basic bit-manipulation extension
RISCV_ISA_Zbkx => true, -- implement cryptography crossbar permutation extension?
RISCV_ISA_Zfinx => true, -- implement 32-bit floating-point extension (using INT regs!)
RISCV_ISA_Zicntr => true, -- implement base counters?
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