From fa69eca405ed4a2ab61d0c85a885128a9e182723 Mon Sep 17 00:00:00 2001
From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com>
Date: Tue, 1 Oct 2024 20:24:08 +0000
Subject: [PATCH 1/3] [Dependabot]: Bump neorv32 from `7e24fce` to `3d71f3e`

Bumps [neorv32](https://github.com/stnolting/neorv32) from `7e24fce` to `3d71f3e`.
- [Release notes](https://github.com/stnolting/neorv32/releases)
- [Commits](https://github.com/stnolting/neorv32/compare/7e24fce6346a93e9d3d58dddeb7f6dbeb2f239b6...3d71f3e20c0dab88e1592b35656a6d92aa67c249)

---
updated-dependencies:
- dependency-name: neorv32
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
---
 neorv32 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/neorv32 b/neorv32
index 7e24fce..3d71f3e 160000
--- a/neorv32
+++ b/neorv32
@@ -1 +1 @@
-Subproject commit 7e24fce6346a93e9d3d58dddeb7f6dbeb2f239b6
+Subproject commit 3d71f3e20c0dab88e1592b35656a6d92aa67c249

From f3a6a5bb1c5483f6fa476400f5461fb139d8737b Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Tue, 1 Oct 2024 22:28:25 +0200
Subject: [PATCH 2/3] [src] update CPU ISA generics

split B ISA extension into sub-extensions
---
 src/neorv32_verilog_wrapper.vhd | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/neorv32_verilog_wrapper.vhd b/src/neorv32_verilog_wrapper.vhd
index 72ba792..9b862ae 100644
--- a/src/neorv32_verilog_wrapper.vhd
+++ b/src/neorv32_verilog_wrapper.vhd
@@ -28,10 +28,11 @@ begin
     INT_BOOTLOADER_EN   => true,        -- boot configuration: boot explicit bootloader
     -- RISC-V CPU Extensions --
     RISCV_ISA_A         => true,        -- implement atomic memory operations extension?
-    RISCV_ISA_B         => true,        -- implement bit-manipulation extension?
     RISCV_ISA_C         => true,        -- implement compressed extension?
     RISCV_ISA_M         => true,        -- implement mul/div extension?
     RISCV_ISA_U         => true,        -- implement user mode extension?
+    RISCV_ISA_Zba       => true,        -- implement shifted-add bit-manipulation extension
+    RISCV_ISA_Zbb       => true,        -- implement basic bit-manipulation extension
     RISCV_ISA_Zbkx      => true,        -- implement cryptography crossbar permutation extension?
     RISCV_ISA_Zfinx     => true,        -- implement 32-bit floating-point extension (using INT regs!)
     RISCV_ISA_Zicntr    => true,        -- implement base counters?

From d18929191427b01fa2e960232ff0d91755884b49 Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Tue, 1 Oct 2024 22:35:33 +0200
Subject: [PATCH 3/3] [.gitmodules] ignore dirty submodules

---
 .gitmodules | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitmodules b/.gitmodules
index 90cfd75..a0e25f6 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,4 @@
 [submodule "neorv32"]
 	path = neorv32
 	url = https://github.com/stnolting/neorv32
+	ignore = dirty