Mixed language simulation

[jeremyherbert]

The main thing which keeps me from using neorv32 in my designs is that I do simulations in verilator (for which VHDL is not supported). I have been trying to work out a way to do mixed language simulation using free tools, and have come up with the following options:

• Drop verilator and use the CXXRTL support in yosys (I’m hoping this is fairly similar to verilator): https://tomverbeure.github.io/2020/11/04/VHDL_Verilog_Cosimulation_with_CXXRTL.html
• Perform synthesis using yosys and then write the netlist to Verilog, then use verilator
• Use vhdlpp (which is part of iverilog) to convert VHDL to verilog

I should clarify that I am trying to simulate the interaction between my own designs and the neorv32 core, rather than debugging the core itself, so I think the netlist output of the core should be ok.

Does anyone have any experience doing this sort of thing? Has anyone tried one of the above strategies with neorv32 (or some other one) ?

[umarcor]

Hi @jeremyherbert! Nice to meet you again 😄

Have a look at ghdl.github.io/ghdl-cosim: VHPIDIRECT » Notebook » How to use GHDL from an external C program?. That is the summary of a dialogue in ghdl/ghdl#1512. It is focused on VHPIDIRECT, but it mentions/explains other solutions, such as the ones mentioned by you.

In microwatt, GHDL and Verilator are used together. The verilog sources are verilated, and executed as a module/component from VHDL, using GHDL as the simulator. Check the Makefile.

Overall, the complexity relies on the fact that each HDL language expects to be the root/kernel of the execution, the one deciding when "simulation time" advances. That is a challenge for any kind of mixed-language simulation, and there is no open source solution available that solves it. Hence, for now we need to translate/convert/transpile VHDL or Verilog to something else.

• CXXRTL deals with a Verilog IR, since GHDL (through ghdl-yosys-plugin) does the VHDL to Verilog conversion. It supports the synthesisable subset only.
• ghdl synth --out=verilog allows converting VHDL to Verilog without requiring Yosys. It supports the synthesisable subset only.
  • vhdlpp might be equivalent to ghdl synth. I did not try it.
• Verilator allows converting Verilog to C/C++, which can be executed from GHDL. Hence, the whole VHDL language is supported, not just the synth subset.

I'd use the last option because I rely on non-synth VHDL features for advanced testing/verification, so other alternatives are not usable for me. However, in your case, since you want to use NEORV32 as a black box, I might suggest to try ghdl synth --out=verilog. That is because, GHDL's synthesis features are already used for generating bitstreams in CI of this repo. Therefore, we know that GHDL supports the NEORV32 codebase. AFAIAA, vhdlpp was not tested yet.

NOTE: there have been attempts to write a "distributed kernel" for mixing multiple HDL/Spice engines. Let me know if you are interested in that topic.