neorv32-examples for Intel FPGA boards

[emb4fun]

Hello,

I have created a neorv32-examples project which can be find here:

https://github.com/emb4fun/neorv32-examples

This project only uses Intel FPGA boards with Quartus. The boards can be find at Terasic.

There are currently examples for the following boards available:

• DE10-Lite (MAX10)
• DE1 (Cyclone II)
• DE0-Nano (Cyclone IV)
• DE0-CV (Cyclone V)
• Cyclone V GX Starter Kit (Cyclone V GX)

My focus is primarily on the support for the external SDRAM memory, i.e. the memory outside the FPGA.

There are examples here where the SDRAM can be addressed directly via the Wishbone bus, and also
examples where access is via the Wishbone to Avalon Master in the Qsys area.

Since I come from the software corner, the other focus is on the area of software debugging. Here
I am using the SEGGER Embedded Studio for RISC-V. A detailed description of how this works is also
planned here in the near future. But that will be available as a little tutorial on my website emb4fun.

Best regards,
Michael

[umarcor]

Nice! This is a very interesting reference for the discussion in #194 and #189.

A minor enhancement: since neorv32 does have at least one submodule, I recommend adding option --recursive to the command in https://github.com/emb4fun/neorv32-examples/blob/master/submodule.txt.

[emb4fun]

Thanks for the info, I've changed now.

[stnolting]

Great project! I am really looking forward to the detailed description of the SEGGER setup!

[emb4fun]

Here now part 1 of the tutorial for creating the DE0-Nano project:

https://www.emb4fun.de/riscv/neorv32/index.html

I currently still have problems with the J-Link EDU and I will give you a note if it works too.

[umarcor]

Very nice work!

[emb4fun]

The problem has now been resolved with the new NOERV32 version 1.6.3.11.
Quickly the data for the J-Link EDU which I have used here:

HW: v11
SW: v7.58b

I will update the example in the next few days.

[stnolting]

-> #216

[emb4fun]

And now the last part, the part about Embedded Studio is online:

https://www.emb4fun.de/riscv/ses4rv/index.html

[stnolting]

So many figures! Really great work!

How about adding (PR) a new section "IDE Integration" to setups/README.md where we could link such example setups? 🤔

[emb4fun]

NEORV32 submodule removed because it will not downloaded in case of "Code > Download ZIP".
That is why NEORV32 has now been integrated directly.

For the easier use of JTAG and a FTDI UART adapter there is now the "JTAG Terasic Adapter"
with Schematic and Gerber files available too.

https://github.com/emb4fun/neorv32-examples

[stnolting]

Nice adapter!
Ever thought about selling some units on tindie.com? I think the DE0-nano board is still a very popular FPGA board, so maybe having such an adapter would be handy for some users.

Btw, I know that most of the Terasic boards have those large pin-headers for custom IO. Are they somehow mutually compatible? I mean things like positions of GND and Vcc, input/output capabilities of the used (by your adapter) FPGA pins, ...

[emb4fun]

All boards I have used here have the GND and VCC lines in the same place.

If someone uses my circuit and Gerber files to sell at Tindie or others, I don't mind
You can do it at your own. I have created this gerber files with a non commercial
version of Eagle an it is not allowed to me to make profit with it.

[emb4fun]

For those who do not want to use a complete IDE, but only need
a debugger, there is now the fourth part of the trilogy, Ozone:

https://www.emb4fun.de/riscv/rv32jlgdb/index.html

That was it for now with the tutorials and I hope that there was
something for everyone.