A question on instruction fetch delay

[mahdi259]

Hi
I have a question on HPMCNT_EVENT_WAIT_DIS event. Can we get real instruction fetch delay from a counter with this event?

It seems that the delay of getting each instruction in pre-fetch buffer is added to it, but predictive approach that fetches next instructions into pre-fetch buffer may result in greater value than real instruction fetch delay (due to control transfer instructions that flush pre-fetch buffer)

[stnolting]

The HPMCNT_EVENT_WAIT_DIS event is triggered when the execution stage is ready to dispatch (and thus execute) a new instruction, but the instruction prefetch buffer is still empty (waiting for the instruction fetch).

Can we get real instruction fetch delay from a counter with this event?

Yes and no. 😅

It seems that the delay of getting each instruction in pre-fetch buffer is added to it, but predictive approach that fetches next instructions into pre-fetch buffer may result in greater value than real instruction fetch delay (due to control transfer instructions that flush pre-fetch buffer)

That is correct.

Let's take an unconditional branch as an example. When executed, the program counter is updated and the prefetch buffer is flushed. Then, a new instruction fetch (using the updated program counter as address) is initiated. The CPU has to send this fetch request to the memory system and wait for the response before the instruction prefetch buffer receives a new instruction that can be dispatched. So in this case the HPMCNT_EVENT_WAIT_DIS tracks

• the instruction fetch request send to the memory system,
• memory wait cycles and
• receiving the instruction fetch response and updating the prefetch buffer.

But you can also obtain HPMCNT_EVENT_WAIT_DIS event when execution computational instructions (that do not alter program flow). The instruction fetch operates in parallel to instruction execution in order to keep the prefetch buffer filled. Sometimes, this is not possible due to bus congestion. In this case, the HPMCNT_EVENT_WAIT_DIS event tracks the number of cycles the instruction fetch has to wait until it is granted bus access.

[mahdi259]

Thanks