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stats.txt
88 lines (87 loc) · 3.48 KB
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stats.txt
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Fetching instrution ['MOVC R10, #2000'] with instruction id:1
Different phase of instructions in clock cycle:1
IF phase of instruction id: 1
Fetching instrution ['MOVC R15, #44'] with instruction id:2
Different phase of instructions in clock cycle:2
ID phase of instruction id:1
IF phase of instruction id: 2
Fetching instrution ['MOVC R0, #232'] with instruction id:3
Different phase of instructions in clock cycle:3
EX phase of instruction id:1
ID phase of instruction id:2
IF phase of instruction id: 3
Fetching instrution ['ADD R6, R0, R15'] with instruction id:4
Different phase of instructions in clock cycle:4
MEM phase of instruction id:1
EX phase of instruction id:2
ID phase of instruction id:3
IF phase of instruction id: 4
Fetching instrution ['MOVC R3, #0'] with instruction id:5
Different phase of instructions in clock cycle:5
WB phase of instruction id:1
<----Instrution id:1 completed at clock cycle:5---->
MEM phase of instruction id:2
EX phase of instruction id:3
ID phase of instruction id:4
IF phase of instruction id: 5
Fetching instrution ['SUB R5, R6, R15'] with instruction id:6
Different phase of instructions in clock cycle:6
WB phase of instruction id:2
<----Instrution id:2 completed at clock cycle:6---->
MEM phase of instruction id:3
EX phase of instruction id:4
ID phase of instruction id:5
IF phase of instruction id: 6
Fetching instrution ['MUL R5, R6, R5'] with instruction id:7
Different phase of instructions in clock cycle:7
WB phase of instruction id:3
<----Instrution id:3 completed at clock cycle:7---->
MEM phase of instruction id:4
EX phase of instruction id:5
ID phase of instruction id:6
IF phase of instruction id: 7
Fetching instrution ['ADD R10, R15, R0'] with instruction id:8
Different phase of instructions in clock cycle:8
WB phase of instruction id:4
<----Instrution id:4 completed at clock cycle:8---->
MEM phase of instruction id:5
EX phase of instruction id:6
ID phase of instruction id:7
IF phase of instruction id: 8
Fetching instrution ['MUL R8, R0, R5'] with instruction id:9
Different phase of instructions in clock cycle:9
WB phase of instruction id:5
<----Instrution id:5 completed at clock cycle:9---->
MEM phase of instruction id:6
EX phase of instruction id:7
ID phase of instruction id:8
IF phase of instruction id: 9
Fetching instrution ['MUL R5, R3, R10'] with instruction id:10
Different phase of instructions in clock cycle:10
WB phase of instruction id:6
<----Instrution id:6 completed at clock cycle:10---->
MEM phase of instruction id:7
EX phase of instruction id:8
ID phase of instruction id:9
IF phase of instruction id: 10
Different phase of instructions in clock cycle:11
WB phase of instruction id:7
<----Instrution id:7 completed at clock cycle:11---->
MEM phase of instruction id:8
EX phase of instruction id:9
ID phase of instruction id:10
Different phase of instructions in clock cycle:12
WB phase of instruction id:8
<----Instrution id:8 completed at clock cycle:12---->
MEM phase of instruction id:9
EX phase of instruction id:10
Different phase of instructions in clock cycle:13
WB phase of instruction id:9
<----Instrution id:9 completed at clock cycle:13---->
MEM phase of instruction id:10
Different phase of instructions in clock cycle:14
WB phase of instruction id:10
<----Instrution id:10 completed at clock cycle:14---->
Different phase of instructions in clock cycle:15
In order pipeline simulation completed with total clock cycle:14
Total number of instruction executed is:10