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Finish 0.1.2
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sunsided committed Jul 2, 2024
1 parent d4febf9 commit 72c132b
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10 changes: 9 additions & 1 deletion CHANGELOG.md
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Expand Up @@ -3,7 +3,15 @@
All notable changes to this project will be documented in this file.
This project uses [Semantic Versioning](https://semver.org/spec/v2.0.0.html).

## [0.1.0] - 2024-07-01
## [0.1.2] - 2024-07-02

[0.1.2]: https://github.com/sunsided/lsm303dlhc-registers/releases/tag/v0.1.2

### Fixed

- Applied some field defaults for `MR_REG_M`, `CRA_REG_M` and `CRB_REG_M`.

## [0.1.1] - 2024-07-01

[0.1.1]: https://github.com/sunsided/lsm303dlhc-registers/releases/tag/v0.1.1

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2 changes: 1 addition & 1 deletion Cargo.toml
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@@ -1,6 +1,6 @@
[package]
name = "lsm303dlhc-registers"
version = "0.1.1"
version = "0.1.2"
authors = ["Markus Mayer <widemeadows@gmail.com>"]
categories = ["embedded", "hardware-support", "no-std", "science::robotics"]
description = "A typed map of the STMicroelectronics LSM303DLHC E-Compass registers"
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8 changes: 4 additions & 4 deletions src/mag.rs
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Expand Up @@ -86,7 +86,7 @@ pub struct ConfigurationARegisterM {

/// Data output rate bits. These bits set the rate at which data is written to all three data
/// output registers.
#[bits(3, access = RW, default = MagOdr::Hz75)]
#[bits(3, access = RW, default = MagOdr::Hz15)]
pub data_output_rate: MagOdr,

/// Must be zero for correct operation of the device.
Expand All @@ -104,7 +104,7 @@ writable_register!(ConfigurationARegisterM, RegisterAddress::CRA_REG_M);
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct ConfigurationBRegisterM {
/// Gain configuration.
#[bits(3, access = RW)]
#[bits(3, access = RW, default = MagGain::Gauss1_3)]
pub gain: MagGain,

/// Must be zero for correct operation of the device.
Expand All @@ -126,14 +126,14 @@ pub struct ModeRegisterM {
zeros_27: u8,

/// Device is placed in sleep mode.
#[bits(1, access = RW)]
#[bits(1, access = RW, default = true)]
pub sleep_mode: bool,

/// Enables single conversion mode.
///
/// * `false` - Continuous conversion mode.
/// * `true` - Single conversion mode.
#[bits(1, access = RW, default = false)]
#[bits(1, access = RW, default = true)]
pub single_conversion: bool,
}

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