Digital logic circuit design with substantial hands-on laboratory work. Algebraic and truth table representation of logic functions and variables. Optimizations of combinational logic, using "don't cares." Multi-level logic optimization. Transistor-level design of logic gates; propagation delay and timing of gates and circuits. The Verilog hardware description language. Memory in digital circuits, including latches, clocked flip-flops, and Static Random Access Memory. Set-up and hold times of sequential logic. Finite state machines - design and implementation. Binary number representation, hardware addition and multiplication. Tri-state gates, and multiplexers. There is a major lab component using Field-Programmable Gate Arrays (FPGAs) and associated computer-aided design software.
Dance of Beavertail involved the use of Verilog for architectural design, input/output management, and conditional trigger creation within the game. It centred on the use of FPGA and VGA display technologies for hardware-based gaming development. Implementation included the integration of image memory storage to facilitate screen transitions at the pixel level. Additionally, the real-time scoring functionality of the game was displayed through a 7-segment display on the FPGA, responding to various inputs, including switches and keys. The process involved rigorous simulation using Logism to validate the Verilog code's functionality before its practical application onto FPGA hardware, facilitated by Quartus for a smooth real-life implementation.
