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Versions of RISC-V that only execute the fib() function.

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riscv-lite

Versions of RISC-V that only execute the fib() function.

Directory structure:

  • fib: contains the fibonacci code
  • csim: simulator written in C
  • jsim: simulator written in Java
  • vsim: simulator written in SystemVerilog (currently does not support memory operations).
  • ecad-labs: simulator built on SystemVerilog with a more sophisticated core.

Build instructions:

For the java simulator, execute the following commands:

$ cd jsim
$ make
$ make run

For the C simulator, execute the following commands:

$ cd csim
$ make
$ ./csim

The vsim simulator does not currently support memory operations, which causes runtime errors. To build it, execute the following commands:

$ cd vsim
$ ./runsim.sh

For the ecad-labs simulator, execute the following commands:

$ cd ecad-labs/clarvi
$ vsim -c -do fib_test.do > run.log
$ grep "f0000000" run.log #This will find the magic output store.

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