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mode_dark_light.py
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mode_dark_light.py
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import json
import math
import os
import platform
import subprocess
import threading
import time
import tkinter
import tkinter.messagebox
from functools import partial
from tkinter import filedialog as fd
import customtkinter
from PIL import Image, ImageTk, ImageFile
import argparse
parser=argparse.ArgumentParser()
parser.add_argument("--theme")
args=parser.parse_args()
customtkinter.set_appearance_mode("dark") # Modes: system (default), light, dark
customtkinter.set_default_color_theme("dark-blue") # Themes: blue (default), dark-blue, green
# CANVAS_BG_COLOR = "#2B2B2B"
CANVAS_BG_COLOR = "#212121"
CANVAS_LINE_COLOR = "white"
if args.theme:
# print(f'Input theme argument: {args.theme}')
if args.theme == 'light':
customtkinter.set_appearance_mode("light") # Modes: system (default), light, dark
customtkinter.set_default_color_theme("dark-blue") # Themes: blue (default), dark-blue, green
CANVAS_BG_COLOR = "#E5E5E5"
CANVAS_LINE_COLOR = "black"
from VectorCGRA.cgra.translate.CGRATemplateRTL_test import *
# importing module
import logging
# Create and configure logger
logging.basicConfig(level=logging.DEBUG,
format='%(asctime)s - %(levelname)s - %(message)s')
PORT_NORTH = 0
PORT_SOUTH = 1
PORT_WEST = 2
PORT_EAST = 3
PORT_NORTHWEST = 4
PORT_NORTHEAST = 5
PORT_SOUTHEAST = 6
PORT_SOUTHWEST = 7
PORT_DIRECTION_COUNTS = 8
ROWS = 4
COLS = 4
INTERVAL = 10
BORDER = 4
MEM_WIDTH = 50
CONFIG_MEM_SIZE = 8
DATA_MEM_SIZE = 4
HIGHLIGHT_THICKNESS = 1
FRAME_LABEL_FONT_SIZE = 15
# FRAME_LABEL_LEVEL_1_FONT_SIZE = FRAME_LABEL_LEVEL_1_FONT_SIZE - 3
def window_size(window, width, height):
window.geometry(f"{width}x{height}")
master = customtkinter.CTk()
master.title("CGRA-Flow: An Integrated End-to-End Framework for CGRA Exploration, Compilation, and Development")
fuTypeList = ["Phi", "Add", "Shift", "Ld", "Sel", "Cmp", "MAC", "St", "Ret", "Mul", "Logic", "Br"]
xbarTypeList = ["W", "E", "N", "S", "NE", "NW", "SE", "SW"]
xbarType2Port = {}
xbarType2Port["W"] = PORT_WEST
xbarType2Port["E"] = PORT_EAST
xbarType2Port["N"] = PORT_NORTH
xbarType2Port["S"] = PORT_SOUTH
xbarType2Port["NE"] = PORT_NORTHEAST
xbarType2Port["NW"] = PORT_NORTHWEST
xbarType2Port["SE"] = PORT_SOUTHEAST
xbarType2Port["SW"] = PORT_SOUTHWEST
xbarPort2Type = {}
xbarPort2Type[PORT_WEST] = "W"
xbarPort2Type[PORT_EAST] = "E"
xbarPort2Type[PORT_NORTH] = "N"
xbarPort2Type[PORT_SOUTH] = "S"
xbarPort2Type[PORT_NORTHEAST] = "NE"
xbarPort2Type[PORT_NORTHWEST] = "NW"
xbarPort2Type[PORT_SOUTHEAST] = "SE"
xbarPort2Type[PORT_SOUTHWEST] = "SW"
xbarPortOpposites = {}
xbarPortOpposites[PORT_WEST] = PORT_EAST
xbarPortOpposites[PORT_EAST] = PORT_WEST
xbarPortOpposites[PORT_NORTH] = PORT_SOUTH
xbarPortOpposites[PORT_SOUTH] = PORT_NORTH
xbarPortOpposites[PORT_NORTHWEST] = PORT_SOUTHEAST
xbarPortOpposites[PORT_NORTHEAST] = PORT_SOUTHWEST
xbarPortOpposites[PORT_SOUTHWEST] = PORT_NORTHEAST
xbarPortOpposites[PORT_SOUTHEAST] = PORT_NORTHWEST
widgets = {}
images = {}
entireTileCheckVar = tkinter.IntVar()
mappingAlgoCheckVar = tkinter.IntVar()
fuCheckVars = {}
fuCheckbuttons = {}
xbarCheckVars = {}
xbarCheckbuttons = {}
kernelOptions = tkinter.StringVar()
kernelOptions.set("Not selected yet")
synthesisRunning = False
constraintFilePath = ""
configFilePath = ""
mapped_tile_color_list = ['#FFF113', '#75D561', '#F2CB67', '#FFAC73', '#F3993A', '#B3FF04', '#C2FFFF']
processOptions = tkinter.StringVar()
processOptions.set("asap7")
class ParamTile:
def __init__(s, ID, dimX, dimY, posX, posY, tileWidth, tileHeight):
s.ID = ID
s.disabled = False
s.posX = posX
s.posY = posY
s.dimX = dimX
s.dimY = dimY
s.width = tileWidth
s.height = tileHeight
s.outLinks = {}
s.inLinks = {}
s.neverUsedOutPorts = set()
s.fuDict = {}
s.xbarDict = {}
s.mapping = {}
for i in range(PORT_DIRECTION_COUNTS):
s.neverUsedOutPorts.add(i)
for xbarType in xbarTypeList:
s.xbarDict[xbarType] = 0
for fuType in fuTypeList:
s.fuDict[fuType] = 1
def hasFromMem(s):
for link in s.inLinks.values():
if not link.disabled and link.isFromMem():
return True
return False
def hasToMem(s):
for link in s.outLinks.values():
if not link.disabled and link.isToMem():
return True
return False
def getInvalidInPorts(s):
invalidInPorts = set()
for port in range(PORT_DIRECTION_COUNTS):
if port not in s.inLinks:
invalidInPorts.add(port)
continue
link = s.inLinks[port]
if link.disabled or type(link.srcTile) == ParamSPM or link.srcTile.disabled:
invalidInPorts.add(port)
continue
return invalidInPorts
def isDefaultFus(s):
for fuType in fuTypeList:
if s.fuDict[fuType] != 1:
return False
return True
def getAllValidFuTypes(s):
fuTypes = set()
for fuType in fuTypeList:
if s.fuDict[fuType] == 1:
if fuType == "Ld" or fuType == "St":
fuTypes.add("Ld")
else:
fuTypes.add(fuType)
return list(fuTypes)
def getInvalidOutPorts(s):
invalidOutPorts = set()
for port in range(PORT_DIRECTION_COUNTS):
if port not in s.outLinks:
invalidOutPorts.add(port)
continue
link = s.outLinks[port]
if link.disabled or type(link.dstTile) == ParamSPM or link.dstTile.disabled:
invalidOutPorts.add(port)
continue
return invalidOutPorts
def reset(s):
s.disabled = False
s.mapping = {}
for i in range(PORT_DIRECTION_COUNTS):
s.neverUsedOutPorts.add(i)
for xbarType in xbarTypeList:
s.xbarDict[xbarType] = 0
for fuType in fuTypeList:
s.fuDict[fuType] = 1
def resetOutLink(s, portType, link):
s.outLinks[portType] = link
s.xbarDict[xbarPort2Type[portType]] = 1
if portType in s.neverUsedOutPorts:
s.neverUsedOutPorts.remove(portType)
def resetInLink(s, portType, link):
s.inLinks[portType] = link
def setOutLink(s, portType, link):
s.outLinks[portType] = link
def setInLink(s, portType, link):
s.resetInLink(portType, link)
# position X/Y for drawing the tile
def getPosXY(s, baseX=0, baseY=0):
return (baseX + s.posX, baseY + s.posY)
# position X/Y for connecting routing ports
def getPosXYOnPort(s, portType, baseX=0, baseY=0):
if portType == PORT_NORTH:
return s.getNorth(baseX, baseY)
elif portType == PORT_SOUTH:
return s.getSouth(baseX, baseY)
elif portType == PORT_WEST:
return s.getWest(baseX, baseY)
elif portType == PORT_EAST:
return s.getEast(baseX, baseY)
elif portType == PORT_NORTHEAST:
return s.getNorthEast(baseX, baseY)
elif portType == PORT_NORTHWEST:
return s.getNorthWest(baseX, baseY)
elif portType == PORT_SOUTHEAST:
return s.getSouthEast(baseX, baseY)
else:
return s.getSouthWest(baseX, baseY)
def getNorthWest(s, baseX=0, baseY=0):
return (baseX + s.posX, baseY + s.posY)
def getNorthEast(s, baseX=0, baseY=0):
return (baseX + s.posX + s.width, baseY + s.posY)
def getSouthWest(s, baseX=0, baseY=0):
return (baseX + s.posX, baseY + s.posY + s.height)
def getSouthEast(s, baseX=0, baseY=0):
return (baseX + s.posX + s.width, baseY + s.posY + s.height)
def getWest(s, baseX=0, baseY=0):
return (baseX + s.posX, baseY + s.posY + s.height // 2)
def getEast(s, baseX=0, baseY=0):
return (baseX + s.posX + s.width, baseY + s.posY + s.height // 2)
def getNorth(s, baseX=0, baseY=0):
return (baseX + s.posX + s.width // 2, baseY + s.posY)
def getSouth(s, baseX=0, baseY=0):
return (baseX + s.posX + s.width // 2, baseY + s.posY + s.height)
def getDimXY(s):
return s.dimX, s.dimY
def getIndex(s, tileList):
if s.disabled:
return -1
index = 0
for tile in tileList:
if tile.dimY < s.dimY and not tile.disabled:
index += 1
elif tile.dimY == s.dimY and tile.dimX < s.dimX and not tile.disabled:
index += 1
return index
class ParamSPM:
def __init__(s, posX, numOfReadPorts, numOfWritePorts):
s.posX = posX
s.ID = -1
s.numOfReadPorts = numOfReadPorts
s.numOfWritePorts = numOfWritePorts
s.disabled = False
s.inLinks = {}
s.outLinks = {}
def getNumOfValidReadPorts(s):
ports = 0
for physicalPort in range(s.numOfReadPorts):
if physicalPort not in s.inLinks:
continue
if s.inLinks[physicalPort].disabled:
continue
ports += 1
return ports
def getNumOfValidWritePorts(s):
ports = 0
for physicalPort in range(s.numOfWritePorts):
if physicalPort not in s.outLinks:
continue
if s.outLinks[physicalPort].disabled:
continue
ports += 1
return ports
def getValidReadPort(s, logicalPort):
port = 0
for physicalPort in range(logicalPort + 1):
if physicalPort not in s.inLinks:
continue
if s.inLinks[physicalPort].disabled:
continue
if physicalPort == logicalPort:
return port
port += 1
return -1
def getValidWritePort(s, logicalPort):
port = 0
for physicalPort in range(logicalPort + 1):
if physicalPort not in s.outLinks:
continue
if s.outLinks[physicalPort].disabled:
continue
if physicalPort == logicalPort:
return port
port += 1
return -1
def getPosX(s, baseX):
return s.posX + baseX
def setInLink(s, portType, link):
s.inLinks[portType] = link
def resetInLink(s, portType, link):
s.setInLink(portType, link)
def setOutLink(s, portType, link):
s.outLinks[portType] = link
def resetOutLink(s, portType, link):
s.setOutLink(portType, link)
class ParamLink:
def __init__(s, srcTile, dstTile, srcPort, dstPort):
s.srcTile = srcTile
s.dstTile = dstTile
s.srcPort = srcPort
s.dstPort = dstPort
s.disabled = False
s.srcTile.resetOutLink(s.srcPort, s)
s.dstTile.resetInLink(s.dstPort, s)
s.mapping = set()
def getMemReadPort(s):
if s.isFromMem():
spm = s.srcTile
return spm.getValidReadPort(s.srcPort)
return -1
def getMemWritePort(s):
if s.isToMem():
spm = s.dstTile
return spm.getValidWritePort(s.dstPort)
return -1
def isToMem(s):
return type(s.dstTile) == ParamSPM
def isFromMem(s):
return type(s.srcTile) == ParamSPM
def getSrcXY(s, baseX=0, baseY=0):
if type(s.srcTile) != ParamSPM:
return s.srcTile.getPosXYOnPort(s.srcPort, baseX, baseY)
else:
dstPosX, dstPosY = s.dstTile.getPosXYOnPort(s.dstPort, baseX, baseY)
spmPosX = s.srcTile.getPosX(baseX)
return spmPosX, dstPosY
def getDstXY(s, baseX=0, baseY=0):
if type(s.dstTile) != ParamSPM:
return s.dstTile.getPosXYOnPort(s.dstPort, baseX, baseY)
else:
srcPosX, srcPosY = s.srcTile.getPosXYOnPort(s.srcPort, baseX, baseY)
spmPosX = s.dstTile.getPosX(baseX)
return spmPosX, srcPosY
class ParamCGRA:
def __init__(s, rows, columns, configMemSize=CONFIG_MEM_SIZE, dataMemSize=DATA_MEM_SIZE):
s.rows = rows
s.columns = columns
s.configMemSize = configMemSize
s.dataMemSize = dataMemSize
s.tiles = []
s.templateLinks = []
s.updatedLinks = []
s.targetTileID = 0
s.dataSPM = None
s.targetAppName = " Not selected yet"
s.compilationDone = False
s.verilogDone = False
s.targetKernels = []
s.targetKernelName = None
s.DFGNodeCount = -1
s.resMII = -1
s.recMII = -1
# return error message if the model is not valid
def getErrorMessage(s):
# at least one tile can perform mem acess
memExist = False
# at least one tile exists
tileExist = False
for tile in s.tiles:
if not tile.disabled:
tileExist = True
# a tile contains at least one FU
fuExist = False
# the tile connect to mem need to able to access mem
if tile.hasToMem() or tile.hasFromMem():
# for now, the compiler doesn't support seperate read or write, both of them need to locate in the same tile
if tile.hasToMem() and tile.hasFromMem() and tile.fuDict["Ld"] == 1 and tile.fuDict["St"] == 1:
memExist = True
else:
return "Tile " + str(tile.ID) + " needs to contain the Load/Store functional units."
for fuType in fuTypeList:
if tile.fuDict[fuType] == 1:
fuExist = True
if not fuExist:
return "At least one functional unit needs to exist in tile " + str(tile.ID) + "."
if not tileExist:
return "At least one tile needs to exist in the CGRA."
if not memExist:
return "At least one tile including a Load/Store functional unit needs to directly connect to the data SPM."
return ""
def getValidTiles(s):
validTiles = []
for tile in s.tiles:
if not tile.disabled:
validTiles.append(tile)
return validTiles
def getValidLinks(s):
validLinks = []
for link in s.updatedLinks:
if not link.disabled and not link.srcTile.disabled and not link.dstTile.disabled:
validLinks.append(link)
return validLinks
def updateFuXbarPannel(s):
targetTile = s.getTileOfID(s.targetTileID)
for fuType in fuTypeList:
if fuType in fuCheckVars:
fuCheckVars[fuType].set(targetTile.fuDict[fuType])
for xbarType in xbarTypeList:
if xbarType in xbarCheckVars:
xbarCheckVars[xbarType].set(targetTile.xbarDict[xbarType])
def initDataSPM(s, dataSPM):
s.dataSPM = dataSPM
def updateMemSize(s, configMemSize, dataMemSize):
s.configMemSize = configMemSize
s.dataMemSize = dataMemSize
def initTiles(s, tiles):
for r in range(s.rows):
for c in range(s.columns):
s.tiles.append(tiles[r][c])
def addTile(s, tile):
s.tiles.append(tile)
def initTemplateLinks(s, links):
numOfLinks = s.rows * s.columns * 2 + (s.rows - 1) * s.columns * 2 + (s.rows - 1) * (s.columns - 1) * 2 * 2
for link in links:
s.templateLinks.append(link)
def resetTiles(s):
for tile in s.tiles:
tile.reset()
for fuType in fuTypeList:
fuCheckVars[fuType].set(tile.fuDict[fuType])
fuCheckbuttons[fuType].configure(state="normal")
for xbarType in xbarTypeList:
xbarCheckVars[xbarType].set(tile.xbarDict[xbarType])
xbarCheckbuttons[xbarType].configure(state="normal")
def enableAllTemplateLinks(s):
for link in s.templateLinks:
link.disabled = False
def resetLinks(s):
for link in s.templateLinks:
link.disabled = False
link.srcTile.resetOutLink(link.srcPort, link)
link.dstTile.resetInLink(link.dstPort, link)
link.mapping = set()
s.updatedLinks = s.templateLinks[:]
for portType in range(PORT_DIRECTION_COUNTS):
if portType in s.getTileOfID(s.targetTileID).neverUsedOutPorts:
xbarCheckbuttons[xbarPort2Type[portType]].configure(state="disabled")
def addTemplateLink(s, link):
s.templateLinks.append(link)
def addUpdatedLink(s, link):
s.updatedLinks.append(link)
def removeUpdatedLink(s, link):
s.updatedLinks.remove(link)
# src = link.srcTile
# src.xbarDict[link.srcPort] = 0
def updateFuCheckbutton(s, fuType, value):
tile = s.getTileOfID(s.targetTileID)
tile.fuDict[fuType] = value
def updateXbarCheckbutton(s, xbarType, value):
tile = s.getTileOfID(s.targetTileID)
tile.xbarDict[xbarType] = value
port = xbarType2Port[xbarType]
if port in tile.outLinks:
tile.outLinks[port].disabled = True if value == 0 else False
def getTileOfID(s, ID):
for tile in s.tiles:
if tile.ID == ID:
return tile
return None
def getTileOfDim(s, dimX, dimY):
for tile in s.tiles:
if tile.dimX == dimX and tile.dimY == dimY:
return tile
return None
# tiles could be disabled due to the disabled links
def updateTiles(s):
unreachableTiles = set()
for tile in s.tiles:
unreachableTiles.add(tile)
for link in s.updatedLinks:
if link.disabled == False and type(link.dstTile) == ParamTile:
if link.dstTile in unreachableTiles:
unreachableTiles.remove(link.dstTile)
if len(unreachableTiles) == 0:
break
for tile in unreachableTiles:
tile.disabled = True
def getUpdatedLink(s, srcTile, dstTile):
for link in s.updatedLinks:
if link.srcTile == srcTile and link.dstTile == dstTile:
return link
return None
# TODO: also need to consider adding back after removing...
def updateLinks(s):
needRemoveLinks = set()
for link in s.updatedLinks:
if link.disabled:
needRemoveLinks.add((link.srcTile, link.dstTile))
for link in s.templateLinks:
link.srcTile.setOutLink(link.srcPort, link)
link.dstTile.setInLink(link.dstPort, link)
s.updatedLinks = s.templateLinks[:]
for tile in s.tiles:
if tile.disabled:
for portType in tile.outLinks:
outLink = tile.outLinks[portType]
dstNeiTile = outLink.dstTile
oppositePort = xbarPortOpposites[portType]
if oppositePort in tile.inLinks:
inLink = tile.inLinks[oppositePort]
srcNeiTile = inLink.srcTile
# some links can be fused as single one due to disabled tiles
if not inLink.disabled and not outLink.disabled and inLink in s.updatedLinks and outLink in s.updatedLinks:
updatedLink = ParamLink(srcNeiTile, dstNeiTile, inLink.srcPort, outLink.dstPort)
s.addUpdatedLink(updatedLink)
s.removeUpdatedLink(inLink)
s.removeUpdatedLink(outLink)
# links that are disabled need to be removed
if inLink.disabled and inLink in s.updatedLinks:
s.removeUpdatedLink(inLink)
if outLink.disabled and outLink in s.updatedLinks:
s.removeUpdatedLink(outLink)
else:
if outLink in s.updatedLinks:
s.removeUpdatedLink(outLink)
for portType in tile.outLinks:
outLink = tile.outLinks[portType]
if outLink in s.updatedLinks:
s.removeUpdatedLink(outLink)
for portType in tile.inLinks:
inLink = tile.inLinks[portType]
if inLink in s.updatedLinks:
s.removeUpdatedLink(inLink)
for link in s.updatedLinks:
if (link.srcTile, link.dstTile) in needRemoveLinks:
link.disabled = True
if type(link.srcTile) == ParamTile:
link.srcTile.xbarDict[xbarPort2Type[link.srcPort]] = 0
def updateSpmOutlinks(s):
spmOutlinksSwitches = widgets['spmOutlinksSwitches']
spmConfigPannel = widgets["spmConfigPannel"]
for switch in spmOutlinksSwitches:
switch.destroy()
for port in paramCGRA.dataSPM.outLinks:
switch = customtkinter.CTkSwitch(spmConfigPannel, text=f"link {port}", command=switchDataSPMOutLinks)
if not paramCGRA.dataSPM.outLinks[port].disabled:
switch.select()
switch.pack(pady=(5, 10))
spmOutlinksSwitches.insert(0, switch)
class ToolTip(object):
def __init__(self, widget):
self.widget = widget
self.tipwindow = None
self.id = None
self.x = self.y = 0
def showtip(self, text):
"Display text in tooltip window"
self.text = text
if self.tipwindow or not self.text:
return
x, y, cx, cy = self.widget.bbox("insert")
x = x + self.widget.winfo_rootx() + 57
y = y + cy + self.widget.winfo_rooty() + 27
# self.tipwindow = tw = tkinter.Toplevel(self.widget)
self.tipwindow = tw = customtkinter.CTkToplevel(self.widget)
tw.wm_overrideredirect(1)
tw.wm_geometry("+%d+%d" % (x, y))
# label = tkinter.Label(tw, text=self.text, justify=tkinter.LEFT,
# background="#ffffe0", relief=tkinter.SOLID, borderwidth=1,
# font=("tahoma", "8", "normal"))
label = customtkinter.CTkLabel(tw, text=self.text)
label.pack(ipadx=1)
def hidetip(self):
tw = self.tipwindow
self.tipwindow = None
if tw:
tw.destroy()
def CreateToolTip(widget, text):
toolTip = ToolTip(widget)
def enter(event):
toolTip.showtip(text)
def leave(event):
toolTip.hidetip()
widget.bind('<Enter>', enter)
widget.bind('<Leave>', leave)
paramCGRA = ParamCGRA(ROWS, COLS, CONFIG_MEM_SIZE, DATA_MEM_SIZE)
def clickTile(ID):
# widgets["fuConfigPannel"].configure(text='Tile ' + str(ID) + ' functional units')
widgets["fuConfigPannel"].configure(label_text='Tile ' + str(ID) + '\nfunctional units')
# widgets["xbarConfigPannel"].config(text='Tile ' + str(ID) + ' crossbar outgoing links')
widgets["xbarConfigPannel"].configure(label_text='Tile ' + str(ID) + '\ncrossbar outgoing links')
widgets["xbarCentralTilelabel"].configure(text='Tile ' + str(ID))
# print(widgets['spmOutlinksSwitches'])
# After clicking the tile, the pannel will fill all directions
# widgets["xbarConfigPannel"].grid(columnspan=4, row=9, column=0, rowspan=3, sticky="nsew")
widgets["entireTileCheckbutton"].configure(text='Disable entire Tile ' + str(ID), state="normal")
# widgets["spmConfigPannel"].grid_forget()
paramCGRA.targetTileID = ID
disabled = paramCGRA.getTileOfID(ID).disabled
for fuType in fuTypeList:
fuCheckVars[fuType].set(paramCGRA.tiles[ID].fuDict[fuType])
fuCheckbuttons[fuType].configure(state="disabled" if disabled else "normal")
for xbarType in xbarTypeList:
xbarCheckVars[xbarType].set(paramCGRA.tiles[ID].xbarDict[xbarType])
xbarCheckbuttons[xbarType].configure(state="disabled" if disabled or xbarType2Port[xbarType] in paramCGRA.tiles[
ID].neverUsedOutPorts else "normal")
entireTileCheckVar.set(1 if paramCGRA.getTileOfID(ID).disabled else 0)
def clickSPM():
print('clickSPM')
# widgets["fuConfigPannel"].config(text='Tile ' + str(paramCGRA.targetTileID) + ' functional units')
# widgets["fuConfigPannelLabel"].configure(text='Tile ' + str(paramCGRA.targetTileID) + ' functional units')
#
# for fuType in fuTypeList:
# fuCheckVars[fuType].set(paramCGRA.tiles[paramCGRA.targetTileID].fuDict[fuType])
# fuCheckbuttons[fuType].configure(state="disabled")
#
# widgets["xbarConfigPannel"].grid_forget()
#
# spmConfigPannel = widgets["spmConfigPannel"]
# spmConfigPannel.config(text='DataSPM outgoing links')
# # After clicking the SPM, the pannel will fill all directions
# spmConfigPannel.grid(row=9, column=0, rowspan=3, columnspan=4, sticky="nsew")
#
# spmEnabledListbox = widgets["spmEnabledListbox"]
# spmDisabledListbox = widgets["spmDisabledListbox"]
#
# widgets["entireTileCheckbutton"].configure(text='Disable entire Tile ' + str(paramCGRA.targetTileID), state="disabled")
def switchDataSPMOutLinks():
spmOutlinksSwitches = widgets['spmOutlinksSwitches']
for portIdx, switch in enumerate(spmOutlinksSwitches):
link = paramCGRA.dataSPM.outLinks[portIdx]
if switch.get():
link.disabled = False
else:
link.disabled = True
def clickSPMPortDisable():
spmEnabledListbox = widgets["spmEnabledListbox"]
portIndex = spmEnabledListbox.curselection()
if portIndex:
port = spmEnabledListbox.get(portIndex)
spmEnabledListbox.delete(portIndex)
widgets["spmDisabledListbox"].insert(0, port)
link = paramCGRA.dataSPM.outLinks[port]
link.disabled = True
def clickSPMPortEnable():
spmDisabledListbox = widgets["spmDisabledListbox"]
portIndex = spmDisabledListbox.curselection()
if portIndex:
port = spmDisabledListbox.get(portIndex)
spmDisabledListbox.delete(portIndex)
widgets["spmEnabledListbox"].insert(0, port)
link = paramCGRA.dataSPM.outLinks[port]
link.disabled = False
def clickEntireTileCheckbutton():
if entireTileCheckVar.get() == 1:
for fuType in fuTypeList:
fuCheckVars[fuType].set(0)
tile = paramCGRA.getTileOfID(paramCGRA.targetTileID)
tile.fuDict[fuType] = 0
# clickFuCheckbutton(fuType)
fuCheckbuttons[fuType].configure(state="disabled")
paramCGRA.getTileOfID(paramCGRA.targetTileID).disabled = True
else:
for fuType in fuTypeList:
fuCheckVars[fuType].set(0)
tile = paramCGRA.getTileOfID(paramCGRA.targetTileID)
tile.fuDict[fuType] = 0
# clickFuCheckbutton(fuType)
fuCheckbuttons[fuType].configure(state="normal")
# paramCGRA.getTileOfID(paramCGRA.targetTileID).disabled = False
def clickFuCheckbutton(fuType):
if fuType == "Ld":
fuCheckVars["St"].set(fuCheckVars["Ld"].get())
paramCGRA.updateFuCheckbutton("St", fuCheckVars["St"].get())
elif fuType == "St":
fuCheckVars["Ld"].set(fuCheckVars["St"].get())
paramCGRA.updateFuCheckbutton("Ld", fuCheckVars["Ld"].get())
paramCGRA.updateFuCheckbutton(fuType, fuCheckVars[fuType].get())
def clickXbarCheckbutton(xbarType):
paramCGRA.updateXbarCheckbutton(xbarType, xbarCheckVars[xbarType].get())
def clickUpdate(root):
rows = int(widgets["rowsEntry"].get())
columns = int(widgets["columnsEntry"].get())
configMemSize = int(widgets["configMemEntry"].get())
dataMemSize = int(widgets["dataMemEntry"].get())
global paramCGRA
oldCGRA = paramCGRA
old_rows_num = paramCGRA.rows
if paramCGRA.rows != rows or paramCGRA.columns != columns:
paramCGRA = ParamCGRA(rows, columns)
# dataSPM = ParamSPM(MEM_WIDTH, rows, rows)
# paramCGRA.initDataSPM(dataSPM)
create_cgra_pannel(root, rows, columns)
# kernel related information and be kept to avoid redundant compilation
paramCGRA.updateMemSize(configMemSize, dataMemSize)
paramCGRA.updateTiles()
paramCGRA.updateLinks()
if old_rows_num != rows:
paramCGRA.updateSpmOutlinks()
paramCGRA.targetAppName = oldCGRA.targetAppName
paramCGRA.compilationDone = oldCGRA.compilationDone
paramCGRA.targetKernels = oldCGRA.targetKernels
paramCGRA.targetKernelName = oldCGRA.targetKernelName
paramCGRA.DFGNodeCount = oldCGRA.DFGNodeCount
paramCGRA.recMII = oldCGRA.recMII
paramCGRA.verilogDone = False
widgets["verilogText"].delete("1.0", tkinter.END)
widgets["resMIIEntry"].delete(0, tkinter.END)
if len(paramCGRA.getValidTiles()) > 0 and paramCGRA.DFGNodeCount > 0:
paramCGRA.resMII = math.ceil((paramCGRA.DFGNodeCount + 0.0) / len(paramCGRA.getValidTiles())) // 1
widgets["resMIIEntry"].insert(0, paramCGRA.resMII)
else:
widgets["resMIIEntry"].insert(0, 0)
def clickReset(root):
rows = int(widgets["rowsEntry"].get())
columns = int(widgets["columnsEntry"].get())
configMemSize = int(widgets["configMemEntry"].get())
dataMemSize = int(widgets["dataMemEntry"].get())
global paramCGRA
oldCGRA = paramCGRA
if paramCGRA.rows != rows or paramCGRA.columns != columns:
paramCGRA = ParamCGRA(rows, columns)
paramCGRA.updateMemSize(configMemSize, dataMemSize)
paramCGRA.resetTiles()
paramCGRA.enableAllTemplateLinks()
paramCGRA.resetLinks()
paramCGRA.updateSpmOutlinks()
create_cgra_pannel(root, rows, columns)
# for _ in range(paramCGRA.rows):
# widgets["spmEnabledListbox"].delete(0)
# widgets["spmDisabledListbox"].delete(0)
# widgets['spmOutlinksSwitches'] = []
# spmOutlinksSwitches = []
# spmConfigPannel = widgets["spmConfigPannel"]
# for port in paramCGRA.dataSPM.outLinks:
# switch = customtkinter.CTkSwitch(spmConfigPannel, text=f"link {port}", command=switchDataSPMOutLinks)
# if not paramCGRA.dataSPM.outLinks[port].disabled:
# switch.select()
# switch.pack(pady=(5, 10))
# spmOutlinksSwitches.insert(0, switch)
# widgets['spmOutlinksSwitches'] = spmOutlinksSwitches
# kernel related information and be kept to avoid redundant compilation
paramCGRA.targetAppName = oldCGRA.targetAppName
paramCGRA.compilationDone = oldCGRA.compilationDone
paramCGRA.targetKernels = oldCGRA.targetKernels
paramCGRA.targetKernelName = oldCGRA.targetKernelName
paramCGRA.DFGNodeCount = oldCGRA.DFGNodeCount
paramCGRA.recMII = oldCGRA.recMII
widgets["verilogText"].delete(0, tkinter.END)
widgets["resMIIEntry"].delete(0, tkinter.END)
if len(paramCGRA.getValidTiles()) > 0 and paramCGRA.DFGNodeCount > 0:
paramCGRA.resMII = math.ceil((paramCGRA.DFGNodeCount + 0.0) / len(paramCGRA.getValidTiles())) // 1
widgets["resMIIEntry"].insert(0, paramCGRA.resMII)
else:
widgets["resMIIEntry"].insert(0, 0)
def clickTest():
# need to provide the paths for lib.so and kernel.bc
os.system("mkdir test")
# os.system("cd test")
os.chdir("test")
widgets["testShow"].configure(text="0%")
master.update_idletasks()
# os.system("pytest ../../VectorCGRA")
testProc = subprocess.Popen(["pytest ../../VectorCGRA", '-u'], stdout=subprocess.PIPE, shell=True, bufsize=1)
failed = 0
total = 0
with testProc.stdout:
for line in iter(testProc.stdout.readline, b''):
outputLine = line.decode("ISO-8859-1")
print(outputLine)
if "%]" in outputLine:
value = int(outputLine.split("[")[1].split("%]")[0])
# print(f'testProgress value: {value}')
widgets["testProgress"].set(value/100)
widgets["testShow"].configure(text=str(value) + "%")
master.update_idletasks()
total += 1
if ".py F" in outputLine:
failed += 1
widgets["testShow"].configure(text=" PASSED " if failed == 0 else str(total - failed) + "/" + str(total))
# (out, err) = testProc.communicate()
# print("check test output:", out)
os.chdir("..")
def clickGenerateVerilog():
message = paramCGRA.getErrorMessage()
if message != "":
tkinter.messagebox.showerror(title="CGRA Model Checking", message=message)
return
os.system("mkdir verilog")
os.chdir("verilog")
# pymtl function that is used to generate synthesizable verilog
cmdline_opts = {'test_verilog': 'zeros', 'test_yosys_verilog': '', 'dump_textwave': False, 'dump_vcd': False,
'dump_vtb': False, 'max_cycles': None}
test_cgra_universal(paramCGRA = paramCGRA)
widgets["verilogText"].delete("1.0", tkinter.END)
found = False
print(os.listdir("./"))
for fileName in os.listdir("./"):
if "__" in fileName and ".v" in fileName:
print("Found the file: ", fileName)
f = open(fileName, "r")
widgets["verilogText"].insert("1.0", f.read())
found = True
break
paramCGRA.verilogDone = True
if not found:
paramCGRA.verilogDone = False
widgets["verilogText"].insert(tkinter.END, "Error exists during Verilog generation")
os.system("mv CGRATemplateRTL__*.v design.v")
# os.system("rename s/\.v/\.log/g *")
os.chdir("..")
def setReportProgress(value):
# widgets["reportProgress"].configure(value=value)
widgets["reportProgress"].set(value/100)
def countSynthesisTime():
global synthesisRunning
timeCost = 0.0