info.yaml

# Tiny Tapeout project information
project:
  title:        "UART Transceiver"      # Project title
  author:       "Saad Khan, Saim Iqbal"      # Your name
  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
  description:  "8 bit data frame, with little endian transmit and receive signals"      # One line description of what your project does
  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
  clock_hz:     50000000       # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_Uart_Transciver"
  
  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
  source_files:
    - "Debouncer.v"
    - "reciver.v"
    - "Transmitter.v"
    - "UART_Transciver_50mhz.v"
    - "Uart_Transciver_Top.v"


# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs data input pins to be transmitted via the transmit signal
  ui[0]: "ui_in[0]"
  ui[1]: "ui_in[1]"
  ui[2]: "ui_in[2]"
  ui[3]: "ui_in[3]"
  ui[4]: "ui_in[4]"
  ui[5]: "ui_in[5]"
  ui[6]: "ui_in[6]"
  ui[7]: "ui_in[7]"

  # Outputs, data ouput pins, displays the data recived bia the recived pin
  uo[0]: "uo_out[0]"
  uo[1]: "uo_out[1]"
  uo[2]: "uo_out[2]"
  uo[3]: "uo_out[3]"
  uo[4]: "uo_out[4]"
  uo[5]: "uo_out[5]"
  uo[6]: "uo_out[6]"
  uo[7]: "uo_out[7]"

  # Bidirectional pins
  uio[0]: "uio_in[0]"  #Transmit_btn
  uio[1]: "uio_in[1]"  #Transmit_switch
  uio[2]: "uio_in[2]"  #uart_rxd
  uio[3]: "uio_out[3]" #TxD
  uio[4]: "uio_out[4]" #uart_rx_break
  uio[5]: "uio_out[5]" #uart_rx_valid
  uio[6]: "uio_out[6]" #high
  uio[7]: "uio_out[7]" #high

# Do not change!
yaml_version: 6