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Fix read/write signal generation via U37 #4

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tomstorey opened this issue Dec 4, 2023 · 1 comment
Open

Fix read/write signal generation via U37 #4

tomstorey opened this issue Dec 4, 2023 · 1 comment
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invalid This doesn't seem right
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cpu-rev3

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@tomstorey
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The input to U37's E pin should probably be the output of an AND gate whos inputs are the UDS/LDS signals, such that (and perhaps most specifically) write is only strobed to a peripheral once one of the xDS signals is asserted.
@tomstorey tomstorey added the invalid This doesn't seem right label Dec 4, 2023
@tomstorey tomstorey added this to the cpu-rev3 milestone Dec 4, 2023
@tomstorey
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Things to keep in mind .. UDS is used to generate XA0, so chip selects for write cycles are delayed until one of the xDS signals is asserted.

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