This project implements a Real-Time Ray-Tracer on a small FPGA.
You can read all about it here.
I also gave a presentation about this at Bang Bang Con West (slides, video).
- A Pano Logic G1 (one with VGA port)
- A JTAG programmer to load the bitstream into the FPGA
If you simply want to run the finished project on your Pano, then all you need to do is load a pre-made bitstream into the device.
The bitstream can be found here.
You don't to resynthesize the bitstream to change the software that runs on the MR1 RISC-V processor.
Once you have made the changes to your C code, just do the following:
cd xilinx
make update_ram
This will update the Pano.bit file with your latest binary.
-
Install RISC-V GCC compiler suite.
See the picorv32 github project on how to do that. It can take a long time to build!
-
Install SpinalHDL.
The actual installation instructions can be found in the VexRisc project.
-
Clone this github repository to
~/projects/rt. -
Build font binary file
cd ~/projects/rt/fonts
make
- Build the firmware. This creates a file called
./sw/progmem8k.bin.
cd ~/projects/rt/sw
make
-
Build the Verilog for synthesis.
When you run this, not only will you create the
Pano.vfile, but also a bunch of.binfile that contain RAM initialization contents, which will be loaded by Xilinx ISE during synthesis
cd ~/projects/rt
make syn
- Fire up Xilinx ISE
cd ~/projects/rt/xilinx
make ise
-
Create the bitstream
- File -> Open Project -> ~/projects/rt/xilinx/xilinx.xise
- Double click on 'Generate Programming File'
-
Fire up Xilinx Impact
cd ~/projects/rt/xilinx
make impact
-
Load bitstream into the device
I have an eye-balling-only simulation set up.
To use it, you first need to make 1 change in the RTL:
Change this line to
val hwMulGlobal = false
After that, just do make sim.
The simulation can take quite a while because it simulates a full frame at 648x480.
To see waveforms, do make waves.
Don't forget to do the hwMulGlobal change before you generate the synthesis Pano.v, because otherwise the design won't fit in the FPGA!