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cputest.cpp
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cputest.cpp
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#include "cputest.h"
#include "cputbl_test.h"
#include "readcpu.h"
#include "disasm.h"
#include "ini.h"
#include "fpp.h"
#include "softfloat/softfloat-specialize.h"
#include "zlib.h"
#include "options.h"
#define MAX_REGISTERS 16
#define EAFLAG_SP 1
#define FPUOPP_ILLEGAL 0x80
static floatx80 fpuregisters[8];
static uae_u32 fpu_fpiar, fpu_fpcr, fpu_fpsr;
struct regtype
{
const TCHAR *name;
uae_u8 type;
};
struct regdata
{
uae_u32 data[3];
uae_u8 type;
};
const int areg_byteinc[] = { 1, 1, 1, 1, 1, 1, 1, 2 };
const int imm8_table[] = { 8, 1, 2, 3, 4, 5, 6, 7 };
int movem_index1[256];
int movem_index2[256];
int movem_next[256];
int hardware_bus_error, hardware_bus_error_fake;
struct mmufixup mmufixup[2];
cpuop_func *cpufunctbl[65536];
cpuop_func_noret *cpufunctbl_noret[65536];
struct cputbl_data
{
uae_s16 length;
uae_s8 disp020[2];
uae_u8 branch;
};
static struct cputbl_data cpudatatbl[65536];
struct regstruct regs;
struct flag_struct regflags;
int cpu_cycles;
static int cycle_count_disable;
static int verbose = 1;
static int feature_exception3_data = 0;
static int feature_exception3_instruction = 0;
static int feature_sr_mask = 0;
static int feature_undefined_ccr = 0;
static int feature_initial_interrupt = 0;
static int feature_initial_interrupt_mask = 0;
static int feature_min_interrupt_mask = 0;
static int feature_loop_mode_cnt = 0;
static int feature_loop_mode_register = -1;
static int feature_loop_mode_68010 = 0;
static int feature_loop_mode_jit = 0;
static int feature_full_extension_format = 0;
static int feature_test_rounds = 2;
static int feature_test_rounds_opcode = 0;
static int feature_flag_mode = 0;
static int feature_usp = 0;
static int feature_exception_vectors = 0;
static int feature_interrupts = 0;
static int feature_waitstates = 0;
static int feature_instruction_size = 0;
static int fpu_min_exponent, fpu_max_exponent, fpu_max_precision, fpu_unnormals;
static int feature_ipl_delay;
static int max_file_size;
static int rnd_seed, rnd_seed_prev;
static TCHAR *feature_instruction_size_text = NULL;
static uae_u32 feature_addressing_modes[2];
static uae_u32 feature_condition_codes;
static int feature_gzip = 0;
static int ad8r[2], pc8r[2];
static int multi_mode;
#define MAX_TARGET_EA 20
static uae_u32 feature_target_ea[MAX_TARGET_EA][3];
static int target_ea_src_cnt, target_ea_dst_cnt, target_ea_opcode_cnt;
static int target_ea_src_max, target_ea_dst_max, target_ea_opcode_max;
static uae_u32 target_ea[3];
static int maincpu[6];
static uae_u8 exceptionenabletable[256];
#define MAX_REGDATAS 32
static int regdatacnt;
static struct regdata regdatas[MAX_REGDATAS];
static uae_u32 ignore_register_mask;
#define HIGH_MEMORY_START (addressing_mask == 0xffffffff ? 0xffff8000 : 0x00ff8000)
// large enough for RTD
#define STACK_SIZE (0x8000 + 8)
#define RESERVED_SUPERSTACK 1024
// space between superstack and USP
#define RESERVED_USERSTACK_EXTRA 128
// space for extra exception, not part of test region
#define EXTRA_RESERVED_SPACE 1024
static uae_u32 test_low_memory_start;
static uae_u32 test_low_memory_end;
static uae_u32 test_high_memory_start;
static uae_u32 test_high_memory_end;
static uae_u32 low_memory_size = 32768;
static uae_u32 high_memory_size = 32768;
static uae_u32 safe_memory_start;
static uae_u32 safe_memory_end;
static int safe_memory_mode;
static uae_u32 user_stack_memory, super_stack_memory;
static uae_u32 user_stack_memory_use;
static uae_u8 *low_memory, *high_memory, *test_memory;
static uae_u8 *low_memory_temp, *high_memory_temp, *test_memory_temp;
static uae_u8 dummy_memory[4];
static uaecptr test_memory_start, test_memory_end, opcode_memory_start;
static uae_u32 test_memory_size;
static int hmem_rom, lmem_rom;
static uae_u8 *opcode_memory;
static uae_u8 *storage_buffer;
static char inst_name[16+1];
static int storage_buffer_watermark_size;
static int storage_buffer_watermark;
static int max_storage_buffer;
static bool out_of_test_space;
static uaecptr out_of_test_space_addr;
static int forced_immediate_mode;
static int test_exception, test_exception_orig;
static int test_exception_extra;
static int exception_stack_frame_size;
static uae_u8 exception_extra_frame[100];
static int exception_extra_frame_size, exception_extra_frame_type;
static uaecptr test_exception_addr;
static int test_exception_3_w;
static int test_exception_3_fc;
static int test_exception_3_size;
static int test_exception_3_di;
static uae_u16 test_exception_3_sr;
static int test_exception_opcode;
static uae_u32 trace_store_pc;
static uae_u16 trace_store_sr;
static int generate_address_mode;
static int test_memory_access_mask;
static uae_u32 opcode_memory_address;
static uaecptr branch_target;
static uaecptr branch_target_pc;
static uae_u16 test_opcode;
static int test_absw;
static uae_u8 imm8_cnt;
static uae_u16 imm16_cnt;
static uae_u32 imm32_cnt;
static uae_u32 immabsw_cnt;
static uae_u32 immabsl_cnt;
static uae_u32 specials_cnt;
static uae_u32 immfpu_cnt;
static uae_u32 addressing_mask;
static int opcodecnt;
static int cpu_stopped;
static int cpu_halted;
static int cpu_lvl = 0;
static int test_count;
static int testing_active;
static uae_u16 testing_active_opcode;
static time_t starttime;
static int filecount;
static uae_u16 sr_undefined_mask;
static int low_memory_accessed;
static int high_memory_accessed;
static int test_memory_accessed;
static uae_u16 extra_or, extra_and;
static struct regstruct cur_regs;
static uae_u16 read_buffer_prev;
static int interrupt_count;
static uaecptr interrupt_pc;
static int interrupt_cycle_cnt, interrupt_delay_cnt;
static int interrupt_level;
static int waitstate_cycle_cnt;
static int waitstate_delay_cnt;
static uaecptr test_instruction_end_pc;
static uaecptr lm_safe_address1, lm_safe_address2;
static uae_u8 ccr_cnt;
static int condition_cnt;
static int subtest_count;
struct uae_prefs currprefs;
struct accesshistory
{
uaecptr addr;
uae_u32 val;
uae_u32 oldval;
int size;
bool donotsave;
};
static int ahcnt_current, ahcnt_written;
static int noaccesshistory = 0;
#define MAX_ACCESSHIST 32000
static struct accesshistory ahist[MAX_ACCESSHIST];
static void pw(uae_u8 *p, uae_u16 v)
{
p[0] = v >> 8;
p[1] = v >> 0;
}
static void pl(uae_u8 *p, uae_u32 v)
{
p[0] = v >> 24;
p[1] = v >> 16;
p[2] = v >> 8;
p[3] = v >> 0;
}
static uae_u32 gl(uae_u8 *p)
{
return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3] << 0);
}
static uae_u32 gw(uae_u8 *p)
{
return (p[0] << 8) | (p[1] << 0);
}
void cputester_fault(void)
{
test_exception = -1;
}
static int is_superstack_use_required(void)
{
switch (testing_active_opcode)
{
case 0x4e73: // RTE
return 1;
}
return 0;
}
static bool valid_address(uaecptr addr, int size, int rwp)
{
int w = (rwp & 0x7fff) == 2;
addr &= addressing_mask;
size--;
if (low_memory_size != 0xffffffff && addr + size < low_memory_size) {
if (addr < test_low_memory_start || test_low_memory_start == 0xffffffff)
goto oob;
// only accept low memory when testing short absolute addressing
if (!test_absw) {
goto oob;
}
// exception vectors needed during tests
if (currprefs.cpu_model == 68000) {
if ((addr + size >= 0x08 && addr < 0x30 || (addr + size >= 0x80 && addr < 0xc0)))
goto oob;
if (feature_interrupts && (addr + size >= 0x60 && addr < 0x80))
goto oob;
}
if (addr + size >= test_low_memory_end)
goto oob;
if (w && lmem_rom)
goto oob;
if (testing_active) {
low_memory_accessed = w ? -1 : 1;
}
return 1;
}
if (high_memory_size != 0xffffffff && addr >= HIGH_MEMORY_START && addr <= HIGH_MEMORY_START + 0x7fff) {
if (addr < test_high_memory_start || test_high_memory_start == 0xffffffff)
goto oob;
if (addr + size >= test_high_memory_end)
goto oob;
// only accept high memory when testing short absolute addressing
if (!test_absw) {
goto oob;
}
if (w && hmem_rom)
goto oob;
if (testing_active) {
high_memory_accessed = w ? -1 : 1;
}
return 1;
}
if (addr >= super_stack_memory - RESERVED_SUPERSTACK && addr + size < super_stack_memory) {
// allow only instructions that have to access super stack, for example RTE
// read-only
if (w) {
goto oob;
}
if (testing_active) {
if (is_superstack_use_required()) {
test_memory_accessed = 1;
return 1;
}
}
goto oob;
}
if (addr >= test_memory_end && addr + size < test_memory_end + EXTRA_RESERVED_SPACE) {
if (testing_active < 0)
return 1;
}
if (addr >= test_memory_start && addr + size < test_memory_end) {
// make sure we don't modify our test instruction
if ((testing_active && w) || (rwp > 0 && (rwp & 0x8000))) {
if (addr >= opcode_memory_start && addr + size < opcode_memory_start + OPCODE_AREA)
goto oob;
}
// don't read data from our test instruction or nop/illegal words. Prefetches allowed.
if (testing_active && (rwp & 1)) {
if (addr >= opcode_memory_start && addr + size < opcode_memory_start + OPCODE_AREA)
goto oob;
}
if (testing_active) {
test_memory_accessed = w ? -1 : 1;
}
return 1;
}
oob:
return 0;
}
static bool check_valid_addr(uaecptr addr, int size, int rwp)
{
if (!valid_address(addr, 1, rwp | 0x8000))
return false;
if (!valid_address(addr + size, 1, rwp | 0x8000))
return false;
return true;
}
static bool is_nowrite_address(uaecptr addr, int size)
{
return addr + size > safe_memory_start && addr < safe_memory_end;
}
static void validate_addr(uaecptr addr, int size)
{
if (valid_address(addr, size, 0))
return;
wprintf(_T(" Trying to store invalid memory address %08x!?\n"), addr);
abort();
}
static uae_u8 *get_addr(uaecptr addr, int size, int rwp)
{
// allow debug output to read memory even if oob condition
if (rwp >= 0 && out_of_test_space)
goto oob;
if (!valid_address(addr, 1, rwp))
goto oob;
if (size > 1) {
if (!valid_address(addr + size - 1, 1, rwp))
goto oob;
}
addr &= addressing_mask;
size--;
// if loop mode: loop mode buffer can be only accessed by loop mode store instruction
if (feature_loop_mode_jit && testing_active && addr >= test_memory_start && addr + size < test_memory_start + LM_BUFFER && (lm_safe_address1 != regs.pc && lm_safe_address2 != regs.pc)) {
goto oob;
}
if (low_memory_size != 0xffffffff && addr + size < low_memory_size) {
return low_memory + addr;
} else if (high_memory_size != 0xffffffff && addr >= HIGH_MEMORY_START && addr <= HIGH_MEMORY_START + 0x7fff) {
return high_memory + (addr - HIGH_MEMORY_START);
} else if (addr >= test_memory_start && addr + size < test_memory_end + EXTRA_RESERVED_SPACE) {
return test_memory + (addr - test_memory_start);
}
oob:
if (rwp >= 0) {
if (!out_of_test_space) {
out_of_test_space = true;
out_of_test_space_addr = addr;
}
}
dummy_memory[0] = 0;
dummy_memory[1] = 0;
dummy_memory[2] = 0;
dummy_memory[3] = 0;
return dummy_memory;
}
static void count_cycles(int cycles)
{
if (cycle_count_disable) {
return;
}
while (cycles > 0) {
cycles--;
cpu_cycles++;
if (interrupt_cycle_cnt != 0) {
bool waspos = interrupt_cycle_cnt > 0;
if (interrupt_cycle_cnt < 0) {
interrupt_cycle_cnt++;
} else {
interrupt_cycle_cnt--;
}
if (interrupt_cycle_cnt == 0) {
if (regs.ipl_pin < IPL_TEST_IPL_LEVEL) {
int ipl = IPL_TEST_IPL_LEVEL;
if (feature_ipl_delay && waspos &&
(((regs.ipl_pin & 1) && !(ipl & 1)) ||
((regs.ipl_pin & 2) && !(ipl & 2)) ||
((regs.ipl_pin & 4) && !(ipl & 4)))) {
interrupt_cycle_cnt = -1;
continue;
}
regs.ipl_pin = IPL_TEST_IPL_LEVEL;
regs.ipl_pin_change_evt = cpu_cycles;
}
if (cpu_cycles == regs.ipl_evt_pre + cpuipldelay2) {
if (regs.ipl_evt_pre_mode) {
ipl_fetch_next();
} else {
ipl_fetch_now();
}
}
interrupt_pc = regs.pc;
interrupt_level = regs.ipl_pin;
interrupt_cycle_cnt = 0;
}
}
}
}
void do_cycles_test(int cycles)
{
if (!testing_active)
return;
count_cycles(cycles);
}
static void add_memory_cycles(uaecptr addr, int c)
{
if (cycle_count_disable) {
return;
}
if (!testing_active) {
return;
}
if (trace_store_pc != 0xffffffff) {
return;
}
if (waitstate_cycle_cnt && (addr & addressing_mask) < 0x200000 && c > 0) {
c *= 2;
while (c > 0) {
int now = cpu_cycles;
int ipl = regs.ipl_pin;
count_cycles(2);
c--;
// wait for free bus cycle
for (;;) {
int cb = (cpu_cycles - waitstate_cycle_cnt) / 2;
// remove init cycles
cb -= 3;
if (cb < 0) {
break;
}
if (feature_waitstates == 1) {
cb %= 3;
// AB-AB-AB-..
if (cb == 2) {
break;
}
} else {
// -BC--BCD-BCD..
// 012301230123
if (cb == 0 || cb == 3) {
break;
}
cb %= 4;
if (cb == 0) {
break;
}
}
ipl = regs.ipl_pin;
count_cycles(2);
}
count_cycles(2);
c--;
if (now == regs.ipl_evt) {
regs.ipl[0] = ipl;
}
}
} else {
c *= 4;
count_cycles(c);
}
}
static void check_bus_error(uaecptr addr, int write, int fc)
{
if (!testing_active)
return;
if (!write && (fc & 2)) {
test_memory_access_mask |= 4;
} else if (!write && !(fc & 2)) {
test_memory_access_mask |= 1;
} else if (write) {
test_memory_access_mask |= 2;
}
if (safe_memory_start == 0xffffffff && safe_memory_end == 0xffffffff)
return;
if (addr >= safe_memory_start && addr < safe_memory_end) {
hardware_bus_error_fake = -1;
if ((safe_memory_mode & 4) && !write && (fc & 2)) {
hardware_bus_error |= 4;
hardware_bus_error_fake |= 1;
} else if ((safe_memory_mode & 1) && !write && !(fc & 2)) {
hardware_bus_error |= 1;
hardware_bus_error_fake |= 1;
} else if ((safe_memory_mode & 2) && write) {
hardware_bus_error |= 2;
hardware_bus_error_fake |= 2;
}
if (!write && (fc & 2) && feature_usp == 3) {
out_of_test_space = true;
out_of_test_space_addr = addr;
}
}
}
static uae_u8 get_ibyte_test(uaecptr addr)
{
check_bus_error(addr, 0, regs.s ? 5 : 1);
uae_u8 *p = get_addr(addr, 1, 4);
add_memory_cycles(addr, 1);
return *p;
}
static uae_u16 get_iword_test(uaecptr addr)
{
check_bus_error(addr, 0, regs.s ? 6 : 2);
if (addr & 1) {
return (get_ibyte_test(addr + 0) << 8) | (get_ibyte_test(addr + 1) << 0);
} else {
uae_u8 *p = get_addr(addr, 2, 4);
add_memory_cycles(addr, 1);
return (p[0] << 8) | (p[1]);
}
}
uae_u32 get_ilong_test(uaecptr addr)
{
uae_u32 v;
check_bus_error(addr, 0, regs.s ? 6 : 2);
if (addr & 1) {
uae_u8 v0 = get_ibyte_test(addr + 0);
uae_u16 v1 = get_iword_test(addr + 1);
uae_u8 v3 = get_ibyte_test(addr + 3);
v = (v0 << 24) | (v1 << 8) | (v3 << 0);
} else if (addr & 2) {
uae_u16 v0 = get_iword_test(addr + 0);
uae_u16 v1 = get_iword_test(addr + 2);
v = (v0 << 16) | (v1 << 0);
} else {
uae_u8 *p = get_addr(addr, 4, 4);
v = (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3]);
add_memory_cycles(addr, 2);
}
return v;
}
uae_u16 get_word_test_prefetch(int o)
{
// no real prefetch
if (cpu_lvl < 2) {
o -= 2;
}
cycle_count_disable = 1;
regs.irc = get_iword_test(m68k_getpci() + o + 2);
cycle_count_disable = 0;
read_buffer_prev = regs.read_buffer;
regs.read_buffer = regs.irc;
uae_u16 v = get_iword_test(m68k_getpci() + o);
return v;
}
static void previoussame(uaecptr addr, int size, uae_u32 *old)
{
if (!ahcnt_current || ahcnt_current == ahcnt_written)
return;
// Move from SR does two writes to same address.
// Loop mode can write different values to same address.
// Mark old values as do not save.
// Also loop mode test can do multi writes and it needs original value.
bool gotold = false;
for (int i = ahcnt_written; i < ahcnt_current; i++) {
struct accesshistory *ah = &ahist[i];
if (((!feature_loop_mode_jit && !feature_loop_mode_68010) || !testing_active) && ah->size == size && ah->addr == addr) {
ah->donotsave = true;
if (!gotold) {
*old = ah->oldval;
gotold = true;
}
}
if (cpu_lvl < 2) {
if (size == sz_long) {
if (ah->size == sz_word && ah->addr == addr) {
ah->donotsave = true;
}
if (ah->size == sz_word && ah->addr == addr + 2) {
ah->donotsave = true;
}
}
}
}
}
void put_byte_test(uaecptr addr, uae_u32 v)
{
if (!testing_active && is_nowrite_address(addr, 1))
return;
if (feature_interrupts >= 2) {
if (addr == IPL_TRIGGER_ADDR) {
add_memory_cycles(addr, 1);
#if IPL_TRIGGER_ADDR_SIZE == 1
interrupt_cycle_cnt = INTERRUPT_CYCLES;
#endif
return;
}
}
check_bus_error(addr, 1, regs.s ? 5 : 1);
uae_u8 *p = get_addr(addr, 1, 2);
if (!out_of_test_space && !noaccesshistory && !hardware_bus_error_fake) {
uae_u32 old = p[0];
previoussame(addr, sz_byte, &old);
if (ahcnt_current >= MAX_ACCESSHIST) {
wprintf(_T(" ahist overflow!"));
abort();
}
struct accesshistory *ah = &ahist[ahcnt_current++];
ah->addr = addr;
ah->val = v & 0xff;
ah->oldval = old & 0xff;
ah->size = sz_byte;
ah->donotsave = false;
}
regs.write_buffer &= 0xff00;
regs.write_buffer |= v & 0xff;
*p = v;
add_memory_cycles(addr, 1);
}
void put_word_test(uaecptr addr, uae_u32 v)
{
if (!testing_active && is_nowrite_address(addr, 1))
return;
if (feature_interrupts >= 2) {
if (addr == IPL_BLTSIZE) {
add_memory_cycles(addr, 1);
waitstate_cycle_cnt = cpu_cycles;
return;
}
if (addr == IPL_TRIGGER_ADDR) {
add_memory_cycles(addr, 1);
#if IPL_TRIGGER_ADDR_SIZE == 2
interrupt_cycle_cnt = INTERRUPT_CYCLES;
#endif
return;
}
}
check_bus_error(addr, 1, regs.s ? 5 : 1);
if (addr & 1) {
put_byte_test(addr + 0, v >> 8);
put_byte_test(addr + 1, v >> 0);
} else {
uae_u8 *p = get_addr(addr, 2, 2);
if (!out_of_test_space && !noaccesshistory && !hardware_bus_error_fake) {
uae_u32 old = (p[0] << 8) | p[1];
previoussame(addr, sz_word, &old);
if (ahcnt_current >= MAX_ACCESSHIST) {
wprintf(_T(" ahist overflow!"));
abort();
}
struct accesshistory *ah = &ahist[ahcnt_current++];
ah->addr = addr;
ah->val = v & 0xffff;
ah->oldval = old & 0xffff;
ah->size = sz_word;
ah->donotsave = false;
}
p[0] = v >> 8;
p[1] = v & 0xff;
}
regs.write_buffer = v;
add_memory_cycles(addr, 1);
}
void put_long_test(uaecptr addr, uae_u32 v)
{
if (!testing_active && is_nowrite_address(addr, 1))
return;
check_bus_error(addr, 1, regs.s ? 5 : 1);
if (addr & 1) {
put_byte_test(addr + 0, v >> 24);
put_word_test(addr + 1, v >> 8);
put_byte_test(addr + 3, v >> 0);
} else if (addr & 2) {
put_word_test(addr + 0, v >> 16);
put_word_test(addr + 2, v >> 0);
} else {
uae_u8 *p = get_addr(addr, 4, 2);
if (!out_of_test_space && !noaccesshistory && !hardware_bus_error_fake) {
uae_u32 old = (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
previoussame(addr, sz_long, &old);
if (ahcnt_current >= MAX_ACCESSHIST) {
wprintf(_T(" ahist overflow!"));
abort();
}
struct accesshistory *ah = &ahist[ahcnt_current++];
ah->addr = addr;
ah->val = v;
ah->oldval = old;
ah->size = sz_long;
ah->donotsave = false;
}
p[0] = v >> 24;
p[1] = v >> 16;
p[2] = v >> 8;
p[3] = v >> 0;
add_memory_cycles(addr, 2);
}
regs.write_buffer = v;
}
static void undo_memory(struct accesshistory *ahp, int end)
{
out_of_test_space = 0;
noaccesshistory = 1;
for (int i = ahcnt_current - 1; i >= end; i--) {
struct accesshistory *ah = &ahp[i];
switch (ah->size)
{
case sz_byte:
put_byte_test(ah->addr, ah->oldval);
break;
case sz_word:
put_word_test(ah->addr, ah->oldval);
break;
case sz_long:
put_long_test(ah->addr, ah->oldval);
break;
}
}
noaccesshistory = 0;
if (out_of_test_space) {
wprintf(_T(" undo_memory out of test space fault!?\n"));
abort();
}
ahcnt_current = end;
}
uae_u32 get_byte_test(uaecptr addr)
{
check_bus_error(addr, 0, regs.s ? 5 : 1);
uae_u8 *p = get_addr(addr, 1, 1);
read_buffer_prev = regs.read_buffer;
regs.read_buffer &= 0xff00;
regs.read_buffer |= *p;
add_memory_cycles(addr, 1);
return *p;
}
uae_u32 get_word_test(uaecptr addr)
{
uae_u16 v;
check_bus_error(addr, 0, regs.s ? 5 : 1);
if (addr & 1) {
v = (get_byte_test(addr + 0) << 8) | (get_byte_test(addr + 1) << 0);
} else {
uae_u8 *p = get_addr(addr, 2, 1);
v = (p[0] << 8) | (p[1]);
}
read_buffer_prev = regs.read_buffer;
regs.read_buffer = v;
add_memory_cycles(addr, 1);
return v;
}
uae_u32 get_long_test(uaecptr addr)
{
uae_u32 v;
check_bus_error(addr, 0, regs.s ? 5 : 1);
if (addr & 1) {
uae_u8 v0 = get_byte_test(addr + 0);
uae_u16 v1 = get_word_test(addr + 1);
uae_u8 v3 = get_byte_test(addr + 3);
v = (v0 << 24) | (v1 << 8) | (v3 << 0);
} else if (addr & 2) {
uae_u16 v0 = get_word_test(addr + 0);
uae_u16 v1 = get_word_test(addr + 2);
v = (v0 << 16) | (v1 << 0);
} else {
uae_u8 *p = get_addr(addr, 4, 1);
v = (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3]);
add_memory_cycles(addr, 2);
}
read_buffer_prev = regs.read_buffer;
regs.read_buffer = v;
return v;
}
uae_u32 get_byte_debug(uaecptr addr)
{
uae_u8 *p = get_addr(addr, 1, -1);
return *p;
}
uae_u32 get_word_debug(uaecptr addr)
{
uae_u8 *p = get_addr(addr, 2, -1);
return (p[0] << 8) | (p[1]);
}
uae_u32 get_long_debug(uaecptr addr)
{
uae_u8 *p = get_addr(addr, 4, -1);
return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3]);
}
uae_u32 get_iword_debug(uaecptr addr)
{
return get_word_debug(addr);
}
uae_u32 get_ilong_debug(uaecptr addr)
{
return get_long_debug(addr);
}
uae_u32 get_byte_cache_debug(uaecptr addr, bool *cached)
{
*cached = false;
return get_byte_test(addr);
}
uae_u32 get_word_cache_debug(uaecptr addr, bool *cached)
{
*cached = false;
return get_word_test(addr);
}
uae_u32 get_long_cache_debug(uaecptr addr, bool *cached)
{
*cached = false;
return get_long_test(addr);
}
uae_u32 sfc_nommu_get_byte(uaecptr addr)
{
return get_byte_test(addr);
}
uae_u32 sfc_nommu_get_word(uaecptr addr)
{
return get_word_test(addr);
}
uae_u32 sfc_nommu_get_long(uaecptr addr)
{
return get_long_test(addr);
}
void dfc_nommu_put_byte(uaecptr addr, uae_u32 v)
{
put_byte_test(addr, v);
}
void dfc_nommu_put_word(uaecptr addr, uae_u32 v)
{
put_word_test(addr, v);
}
void dfc_nommu_put_long(uaecptr addr, uae_u32 v)
{
put_long_test(addr, v);
}
uae_u16 get_wordi_test(int o)
{
uae_u32 v = get_word_test_prefetch(o);
regs.pc += 2;
return v;
}
uae_u32 memory_get_byte(uaecptr addr)
{
return get_byte_test(addr);
}
uae_u32 memory_get_word(uaecptr addr)
{
return get_word_test(addr);
}
uae_u32 memory_get_wordi(uaecptr addr)
{
return get_iword_test(addr);
}
uae_u32 memory_get_long(uaecptr addr)
{
return get_long_test(addr);
}
uae_u32 memory_get_longi(uaecptr addr)
{
return get_ilong_test(addr);
}
void memory_put_long(uaecptr addr, uae_u32 v)
{
put_long_test(addr, v);
}
void memory_put_word(uaecptr addr, uae_u32 v)
{
put_word_test(addr, v);
}
void memory_put_byte(uaecptr addr, uae_u32 v)
{
put_byte_test(addr, v);
}
uae_u8 *memory_get_real_address(uaecptr addr)
{
return NULL;
}
uae_u32 next_iword_test(void)
{
uae_u32 v = get_word_test_prefetch(0);
regs.pc += 2;
return v;
}
uae_u32 next_ilong_test(void)
{
uae_u32 v = get_word_test_prefetch(0) << 16;
v |= get_word_test_prefetch(2);
regs.pc += 4;
return v;
}
bool mmu_op30(uaecptr pc, uae_u32 opcode, uae_u16 extra, uaecptr extraa)
{
m68k_setpc(pc);
op_illg_noret(opcode);
return true;
}
bool is_cycle_ce(uaecptr addr)
{
return 0;
}
void ipl_fetch_next_pre(void)
{
ipl_fetch_next();
regs.ipl_evt_pre = cpu_cycles;
regs.ipl_evt_pre_mode = 1;
}
void ipl_fetch_now_pre(void)
{
ipl_fetch_now();
regs.ipl_evt_pre = cpu_cycles;
regs.ipl_evt_pre_mode = 0;
}
// ipl check was early enough, interrupt possible after current instruction
void ipl_fetch_now(void)
{
int c = cpu_cycles;
regs.ipl_evt = c;
regs.ipl[0] = regs.ipl_pin;
regs.ipl[1] = 0;
}
// ipl check was too late, interrupt possible after following instruction
void ipl_fetch_next(void)
{
int c = cpu_cycles;
if (c - regs.ipl_pin_change_evt >= cpuipldelay4) {
regs.ipl[0] = regs.ipl_pin;
regs.ipl[1] = 0;
} else {
regs.ipl[1] = regs.ipl_pin;
}
}
int intlev(void)
{
return interrupt_level;
}
void do_cycles_stop(int c)
{
do_cycles_test(c);
}
uae_u32(*x_get_long)(uaecptr);
uae_u32(*x_get_word)(uaecptr);
uae_u32(*x_get_byte)(uaecptr);
void (*x_put_long)(uaecptr, uae_u32);
void (*x_put_word)(uaecptr, uae_u32);
void (*x_put_byte)(uaecptr, uae_u32);