(Verilog+FPGA EGO1) (140/100) A real car: our project of CS207 2022 Fall: Digital Logic Design, SUSTech. Taught by Prof. James YU @James-Yu.
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Updated
Feb 22, 2023 - Verilog
(Verilog+FPGA EGO1) (140/100) A real car: our project of CS207 2022 Fall: Digital Logic Design, SUSTech. Taught by Prof. James YU @James-Yu.
(1080/1000) Labs of CS203 2022 Fall: Data Structure and Algorithm Analysis, SUSTech. Taught by Prof. Bo TANG @tangloner.
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