Skip to content
#

4-bit-parallel-adder

Star

Here is 1 public repository matching this topic...

Vedant-02 / Verilog-HDL-Lab-Experiments

Star 3

Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

verilog hacktoberfest barrel-shifter full-adder carry-look-ahead-adder 4-bit-comparator carry-select-adder adder-subtractor bcd-adder binary-multiplier binary-to-gray hacktoberfest2022 32-bit-alu priority-encoder 4-bit-parallel-adder 4-bit-combinational-adder bcd-to-7-segment 32-bit-fast-adder carry-skip-adder bcd-subtractor
  • Updated Oct 23, 2022
  • Verilog

Improve this page

Add a description, image, and links to the 4-bit-parallel-adder topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the 4-bit-parallel-adder topic, visit your repo's landing page and select "manage topics."

Learn more