Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

Verilog code to replace the Commodore SDMAC found in the A3000

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls

This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.

A basic implementation of the RISCV core into a DE10nano FPGA board.

Graph Processing Framework that supports || OpenMP || CAPI

FPGA implementation of the popular logic game using VHDL and Altera DE1

Research & Development FPGA projects for different boards

An 8-bit processor in VHDL based on a simple instruction set

Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

ECE385 @ UIUC FA22

This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.

Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract

This repo is the lab materials for NTUEE DCLAB (http://dclab.ee.ntu.edu.tw).

Implementation of an Edge Detection Filter Using the Avalon Interface

FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA

Laboratório de Arquitetura de Sistemas Digitais, ministrado pelo professor Rafael Bezerra Correia Lima. Foram desenvolvidos 8 requisitos de hardware, 1 requisito de software e 1 projeto de disciplina que totalizam 10 Sprints. A arquitetura de sistemas implementada é baseada em MIPS 8 bits, e desenvolvidos e testados na FGPA Ciclone II EP2C35F672C6

Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.