AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

An AXI4 crossbar implementation in SystemVerilog

Basic USB 1.1 Host Controller for small FPGAs

AXI4 and AXI4-Lite interface definitions

Audio controller (I2S, SPDIF, DAC)

USB -> AXI Debug Bridge

HLS for Networks-on-Chip

Master and Slave made using AMBA AXI4 Lite protocol.

Multi-port BRAM IP for ASIC and FPGA

VHDL generator from SystemRDL

A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)

A collection of formal properties for hardware buses, and cores using them.

OLED driver demo running on ZedBoard

Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)

A Custom AXI4 SPI Peripheral

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

Hardware implementation of a base 2 logarithm

AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.