AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
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Updated
Dec 7, 2024 - VHDL
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
AXI4 and AXI4-Lite interface definitions
A collection of formal properties for hardware buses, and cores using them.
A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
A 2x2 mesh NoC compatible with AXI streaming interface
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