比做算法的懂工程落地，比做工程的懂算法模型。
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Dec 22, 2024 - Jupyter Notebook
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chip-design
Here are 12 public repositories matching this topic...
Parametric layout generator for digital, analog and mixed-signal integrated circuits
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Dec 20, 2024 - C
Skywater 130nm Klayout Device Generators PDK
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Jul 12, 2024 - Python
Conda + KLayout
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Aug 21, 2022 - Dockerfile
Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah
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Oct 19, 2024
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
vhdl verilog microprocessor hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator asic-design chip-design 5-stage-pipelined-processor rv32i-processor
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Mar 22, 2024 - Verilog
xspcomm encapsulates the DPI-based digital circuit and provides various high-level language operation interfaces.
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Dec 27, 2024 - C++
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
verification matrix-multiplication verilog systemverilog questasim logic-design sva systolic-arrays amba-apb functional-coverage chip-design
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Jun 26, 2024 - Verilog
Carleton University / ELEC4609 - Integrated Circuit Design and Fabrication / Project: Static Logic PRSG (Pseudo Random Sequence Generator) chip design, fabrication and testing.
carleton-university chip-design pseudo-random-sequence-generator chip-fabrication chip-testing elec4609
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Aug 6, 2024
Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) architecture. Open NPU aims to democratize access to cutting-edge neural processing technology for machine learning and AI applications.
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Jun 20, 2024
VHDL Projects that I've created during the course Programmable Logic Devices in West Pomeranian University of Technology in Szczecin.
mux comparator seven-segment traffic-light-controller chip-design digtial-design adder-circuit line-buffer ring-counter four-digit-seven-segment-driver
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May 30, 2022 - VHDL
Final Project for Digital Integrated Circuits. SoupVenture Chip.
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Dec 18, 2024 - Verilog
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