TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

The Mythical CPU Simulator for Real Students

A software simulator of how an OS might schedule processes

Implementation of Utility based cache partitioning research paper in Champsim simulator

This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.

CPU Simulator written in Python

Simulator for the MIC-1 CPU described in Andrew S. Tanenbaum’s textbook Structured Computer Organization

💡 WepSIM: Web Elemental Processor SIMulator 📱 💻 🖥️

Visualizes/animates the dataflow between RAM and CPU components while running a short assembly program of your choice

A simple implementation of RISC-V CPU simulator

A Java program with a GUI that simulates a custom CPU. One can load instructions in a custom assembler language and see the registries' changes.

Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL

Simple Web-based 16-bit Microprocessor Assembler Simulator (8085 Working Progress)

An experimental Instruction Set Architecture (ISA) and the implementation of a CPU simulator and an assembler.

Simulating the architecture of a computer in the terminal (Assembler + Simulator)

A small and simple 8-bit CPU built in Logisim. The project also includes an assembler and a manual for those who want to learn how a processor works.

Tera - A simulated ternary (base 3) CPU, assembly language, assembler and decompiler. Uses trytes made up of 9 trits rather than bytes of 8 bits.

An educational resource that enables students to better visualize the execution of assembly code

A Y86-64 processor simulator written in JavaScript (Node.js) and C++11

MIPS CPU Implementation using VHDL