Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs
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Updated
Jun 4, 2024 - Python
Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs
Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide
A collection of Verilog code examples, perfect for beginners or anyone looking to learn Verilog. These examples are based on my homework assignments from my university and include comments and explanations to help you understand the code better. Check out the link below for more information about Verilog!! 👇
Intel Quartus Prime Synthesis Engine for Docker
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA
VHDL programming about basic N-bit binary calculator ( + - x / ) for altera fpga cyclone v board
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
This is my bachelor's degree project. I have used a FPGA to modify audio signal and create different sounds, like distortion, overdrive, echo, reverb...
Sends data from an ADC to a UART-USB interface
Various lessons learned while designing an OV5640 camera display in VHDL/Embedded Linux on a Cyclone V SOC board
Implement HDMI output using only SystemVerilog and an Analog Devices ADV7513
🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
This repository contains Quartus projects using VHDL that can be used to learn the basics of language and FPGA or just simply in the projects. All the codes are written intentionally in very easy way so that one can actually understand the language. This repository was made to help beginners in the VHDL language or for people who are using FPGA …
Verilog RISC Processor Design
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