A simple "database" that use JSON file for Node.JS.

loxilb ebpf sub-module

A 32-bit MIPS processor used Altera Quartus II with Verilog.

A Hybrid Framework to Build High-performance Adaptive Neural Networks for Kernel Datapath

CSE-306-Computer-Architecture Offline / Assignment on ALU, Floating Point Adder and 8 bit MIPS Datapath along with pipelining

simulating connection of micro processor and accelerator on a bus context with systemc language

Design and implementation of a complete ARM based CPU.

This project is a Computer Architecture Design and Data Path Simulator which simulates a modified MIPS datapath with pipelining written in Java.

EE89H Final Project

The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.

A full datapath made in Logisim. Made in the first bachelor of computer science at the University of Antwerp.

Assignment from the Advanced Computer Architecture class.

Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).

4 staged MIPS verilog processor

Digital circuit description to perform multiplication with data_path and control_path using verilog

Calculadora eletrônica feita no simulador Circuit Verse, realiza soma de 2 números de 0 a 99, conversão bin2dec e dec2bin.

Repository regarding the Practical Works of the Computer Organization discipline

A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.