arc-research-lab / CHARM Star 124 Code Issues Pull requests CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture fpga deeplearning design-space-exploration versal high-level-synthesis electronic-design-automation heterogeneous-computing acap domain-specific-architecture versalacap Updated Jan 13, 2025 C++
arc-research-lab / AIM Star 22 Code Issues Pull requests AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)! design-space-exploration versal high-level-synthesis electronic-design-automation heterogeneous-computing acap domain-specific-architecture versalacap Updated Sep 29, 2024 C++
DanieleParravicini / regex_coprocessor Star 7 Code Issues Pull requests An accelerator to which you can offload RE matching and that does not use backtracking fpga regular-expression pynq-z1 architectures ultra96 ultra96-v2 domain-specific-architecture Updated Sep 18, 2021 VHDL